DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Examiner acknowledges submission of the amendment and arguments filed on March 4, 2026. Claims 1-12 are currently pending in this application. Claim 1 has been amended. The examiner withdraws the objections to the specification due to Applicant's amendment.
The title of the invention has been amended by the Applicant and reads as follows “Electrostatic Discharge Protection Circuit with Detection Circuit and Discharge Circuit”. The new title of the invention is acceptable and indicative of the invention to which the claims are directed.
Examination Notice
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Gauthier (US 7,274,546 B2).
With regard to claim 1, Gauthier teaches an electrostatic discharge protection circuit (200 – Fig. 2) coupled to a first power bonding pad (P10 – Fig. 2; see annotated figure below), comprises:
a detection circuit (10 – Fig. 2; see annotated figure below), coupled to the first power bonding pad (P10 – Fig. 2; see annotated figure below), detecting whether an electrostatic discharge event occurs on the first power bonding pad (P10 – Fig. 2; see annotated figure below) to generate a first detection signal (col. 4, lines 14-29; signal to render the first P-type transistor (PFET) conductive) and a second detection signal (col. 4, lines 52-61; signal to activate the first N-type transistor (NFET));
a first P-type transistor (PFET – Fig. 2; see annotated figure below) having a first electrode (see first electrode of PFET – Fig. 2; see annotated figure below) coupled to the first power bonding pad (P10 – Fig. 2; see annotated figure below), a second electrode (see second electrode of PFET – Fig. 2; see annotated figure below) coupled to a first node (N13 – Fig. 2; see annotated figure below), and a control electrode (see gate of PFET – Fig. 2; see annotated figure below) receiving the first detection signal (col. 4, lines 14-29; signal to render the first P-type transistor (PFET) conductive);
a first N-type transistor (NFET – Fig. 2; see annotated figure below) having a first electrode (see first electrode of NFET – Fig. 2; see annotated figure below) coupled to the first node (N13 – Fig. 2; see annotated figure below), a second electrode (see second electrode of NFET – Fig. 2; see annotated figure below) coupled to a second power bonding pad (P11 – Fig. 2; see annotated figure below), and a control electrode (see gate of NFET – Fig. 2; see annotated figure below) receiving the second detection signal (col. 4, lines 52-61; signal to activate the first N-type transistor (NFET)) which is different from the first detection signal (col 4, lines 14-29; 52-61), wherein a first control signal (col. 4, lines 14-61; control signal to turning on 206 – Fig. 2) is generated on the first node (N13 – Fig. 2; see annotated figure below); and
a discharge circuit (206 – Fig. 2) coupled between the first power bonding pad (P10 – Fig. 2; see annotated figure below) and the second power bonding pad (P11 – Fig. 2; see annotated figure below) and controlled by the first control signal (control signal to turning on 206 – Fig. 2),
wherein in response the electrostatic discharge event (col. 4, lines 14-15) occurring on the first power bonding pad (P10 – Fig. 2; see annotated figure below), the discharge circuit (206 – Fig. 2) provides a discharge path (path between P10 and P11 – Fig. 2; see annotated figure below) between the first power bonding pad (P10 – Fig. 2; see annotated figure below) and the second power bonding pad (P11 – Fig. 2; see annotated figure below) according to the first control signal (col. 4, lines 14-61).
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Gauthier (US 7,274,546 B2) – Annotated Fig. 2
Allowable Subject Matter
Claim(s) 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regard to claim 2, Gauthier (US 7,274,546 B2) teaches the detection circuit (10 – Fig. 2; see annotated figure above) comprises: a first resistor (R1 – Fig. 2) (col. 3, lines 50-53) coupled between the first power bonding pad (P10 – Fig. 2; see annotated figure above) and a second node (N10 – Fig. 2; see annotated figure above); a first capacitor (R1 – Fig. 2) coupled between the second node (N10 – Fig. 2; see annotated figure above) and the second power bonding pad (P11 – Fig. 2; see annotated figure above). But, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a second capacitor coupled between the first power bonding pad and a third node; a second resistor coupled between the third node and the second power bonding pad; and an inverter circuit coupled between a power terminal and the second power bonding pad, wherein the first detection signal is generated at the second node, and the inverter circuit generates the second detection signal.”
Claim(s) 3-8 are allowed by dependence on claim 2.
With regard to claim 9, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a power state control circuit coupled between the first node and the second power bonding pad and controlled by a second control signal, wherein the power state control circuit determines whether a conductive path is provided between the first node and the second power bonding pad according to the second control signal.”
Claim(s) 10-12 are allowed by dependence on claim 9.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Wang (US 2015/0295399 A1) teaches a1 false-trigger free power-rail ESD clamp protection circuit, wherein the circuit comprises an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel; the ESD impact detection component comprises NMOS transistors Mcn1 and Mcn2, a capacitor C1 and a resistor R1; the discharge transistor is NMOS transistor Mbig; the discharge transistor turn-on channel comprises PMOS transistors Mp2-1, Mp2-2 and Mp3 and an NMOS transistor Mn2; and the discharge transistor shutoff channel comprises PMOS transistors Mp4, Mp5 and Mp6, NMOS transistors Man1, Man2, Mbn1, Mbn2, Mn3, Mn4-1 and Mn4-2, and capacitors C2 and C3.
Lin (US 12,444,935 B2) teaches an electrostatic discharge protection circuit coupled to a first bonding pad, comprising: an electrostatic discharge detection circuit detecting whether an electrostatic discharge event occurs on the first bonding pad to generate a detection signal on a first node; a P-type transistor comprising a source coupled to the first bonding pad, a drain coupled to a second node, and a gate coupled to the first node to receive the detection signal; a first N-type transistor comprising a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second bonding pad; and a discharge circuit coupled between the first bonding pad and the ground and controlled by a driving signal on the second node; wherein in response to that the electrostatic discharge protection circuit is in an operation mode, the first bonding pad receives a first voltage, and the second bonding pad receives a second voltage.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
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