Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 41 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In the instant case, Claim 41 discloses “The method of claim 21, wherein providing the signal distribution structure on the first carrier comprises:
forming a second conductive layer “123” over the first carrier “110”;
forming the first dielectric layer “111” such that a bottom side of the first dielectric layer is on a top side of the second conductive layer “123”;
forming the opening through the first dielectric layer 111 to expose a top side the second conductive layer 123; and
forming the first conductive layer “121” over a top side of the first dielectric layer 111 and the opening such that the bottom side of the first conductive layer extends through the opening and contacts the top side of the second conductive layer.” According to the specification of the instant application, referring to FIGS. 2 and 9 the carrier wafer 110/310, the first dielectric layer is 111/311, first conductive layer is 121/321 and the second conductive layer is 123/323, while the second dielectric layer is 122/322. This is contrary to what the claim is stating that “forming the opening through the first dielectric layer to expose a top side the second conductive layer”. The first dielectric layers 111/311 do not have any via formed therein to expose the second conductive layer, since the second conductive layers 123/323 are formed on the first dielectric layer. This is inconsistent with disclosed invention as to enable one of ordinary skill in the art, prior to the effective filing date of the instant application to make or use to the disclosed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 41 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the instant case, Claim 41 discloses “The method of claim 21, wherein providing the signal distribution structure on the first carrier comprises:
forming a second conductive layer “123” over the first carrier “110”;
forming the first dielectric layer “111” such that a bottom side of the first dielectric layer is on a top side of the second conductive layer “123”;
forming the opening through the first dielectric layer 111 to expose a top side the second conductive layer 123; and
forming the first conductive layer “121” over a top side of the first dielectric layer 111 and the opening such that the bottom side of the first conductive layer extends through the opening and contacts the top side of the second conductive layer.” According to the specification of the instant application, referring to FIGS. 2 and 9 the carrier wafer 110/310, the first dielectric layer is 111/311, first conductive layer is 121/321 and the second conductive layer is 123/323, while the second dielectric layer is 122/322. This is contrary to what the claim is stating that “forming the opening through the first dielectric layer to expose a top side the second conductive layer”. The first dielectric layers 111/311 do not have any via formed therein to expose the second conductive layer, since the second conductive layers 123/323 are formed on the first dielectric layer. This is inconsistent with disclosed invention an render the claimed invention indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 2016/0064328), (hereinafter, Kwon).
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RE Claim 21, Kwon discloses a stacked silicon interconnect product and method of making the same. Kwon discloses a method of manufacturing an electronic device, the method comprising:
providing a signal distribution structure 102 “interposer” on a first carrier 202, the signal distribution structure comprising one or more conductive layers 104 “metallization layer” and one or more dielectric layers 108, referring to FIG. 2A, wherein a bottom side of a first conductive layer “upper metallization layer 104” of the one or more conductive layers 104 is on top side of a first dielectric layer 108 of the one or more dielectric layers 108, “of the upper/lower metallization layers 104”, and wherein the bottom side of the first conductive layer “upper metallization layer 104” extends through an opening of the first dielectric layer 108 “of the lower metallization layer 104 of the dielectric layer 108, referring to annotated FIG. 2D above;
coupling a bottom side of a semiconductor component 110 “integrated circuit” to the one or more conductive layers 104 of the signal distribution structure 102 “interposer”, referring to FIG. 2B;
encapsulating lateral sides of the semiconductor component 110 in an encapsulating material 117 “mold encapsulation”, referring to FIG. 2C;
attaching a second carrier “structural substrate” 121 to the encapsulating material 117, referring to FIG. 2D;
removing the first carrier 202 from the signal distribution structure 102 “interposer”, referring to FIG. 2E; and
providing interconnection structures 114/120 that are coupled to the one or more conductive layers via 104 a bottom side of the signal distribution structure 102 “interposer”, referring to FIG. 2F.
RE Claim 22, Kwon discloses a method, wherein the providing the signal distribution structure 102 “interposer” on the first carrier comprises 202 forming the one or more conductive layers 103 and the one or more dielectric layers 108 of the signal distribution structure 102 “interposer” on a top side of the first carrier 202, referring to FIG. 2A.
RE Claim 23, Kwon discloses a method, wherein:
the signal distribution structure 102 “interposer” comprises conductive pads “landing pads” [0022] on a top side of the signal distribution structure 102 “interposer” and coupled to the one or more conductive layers 104 [0022], referring to FIG. 1; and
the coupling the bottom side of the semiconductor component to the one or more conductive layers comprises coupling conductive bumps 114 along the bottom side of the semiconductor component 110 “integrated circuit” to the conductive pads “landing pads” [0022].
RE Claim 24, Kwon discloses a method, comprising:
providing under bump metal 114 on the bottom side of the signal distribution structure 102 “interposer, referring to FIG. 2F; and
wherein the providing the interconnection structures 410a/410b “micro-bump assembly”, referring to FIGS. 4A/4B comprises providing the interconnection structures “landing pads” 410a/410b on the under-bump metal [0034-0042].
RE Claim 25, Kwon discloses a method, wherein the coupling the bottom side of the semiconductor component 110 comprises coupling the bottom side of the semiconductor component 110 to the one or more conductive layers via conductive attachment structures 410a/410b, referring to FIGS. 4A/4B.
RE Claim 26, Kwon discloses a method, wherein the encapsulating 117/116 the lateral sides of the semiconductor component 110 underfills the bottom side of the semiconductor component such that the encapsulating material encapsulates the conductive attachment structures 114 [0023]. Examiner notes that the underfill material 116 encapsulating the conductive attachment structures 114 is formed of a similar material as the epoxy-based encapsulant material 117 [0023], hence meeting the claimed limitation.
RE Claim 27, Kwon discloses a method, comprising providing an underfill material 116 between the bottom side of the semiconductor component 110 and the top side of the signal distribution structure 102 “interposer” such that the underfill material 116 encapsulates the conductive attachment structures 114.
RE Claim 28, Kwon discloses a method, wherein the encapsulating 117 the lateral sides of the semiconductor component encapsulate the underfill material 116 with the encapsulating material 117, referring to FIGS. 2C-2F.
RE Claim 29, Kwon discloses a method, wherein the removing the first carrier 202 comprises:
grinding away a first portion of the first carrier; and
etching away a second portion of the first carrier, referring to FIGS. 2D-2E [0031].
Response to Arguments
Applicant's arguments filed 02/02/2026 have been fully considered but they are not persuasive. In the instant case, the annotated FIG. 2D above clearly shows that the signal distribution structure 102 “interposer” on a first carrier 202, the signal distribution structure comprising one or more conductive layers 104 “metallization layer” and one or more dielectric layers 108, referring to FIG. 2A, wherein a bottom side of a first conductive layer “upper metallization layer 104” of the one or more conductive layers 104 is on top side of a first dielectric layer 108 of the one or more dielectric layers 108, “of the upper/lower metallization layers 104”, and wherein the bottom side of the first conductive layer “upper metallization layer 104” extends through an opening of the first dielectric layer 108 “of the lower metallization layer 104 of the dielectric layer 108.
Furthermore, Kwon discloses that the metal segments 106 of the interposer maybe “vias”, i.e. holes or opening [0022]. This implies that the dielectric layer 108 must be formed first, subsequently an etch process is performed to form vias that will be filled with the metal segment 106.
Applicant is encouraged to review Huemoeller et al. (US 2019/0287818) disclosure per explanation below in the conclusion for further insight.
Therefore, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Huemoeller et al. (US 2019/0287818) discloses a method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution. Furthermore, Huemoeller et al. disclose forming a first dielectric layer 30 “solder mask” over a carrier substrate 120 and circuit traces 24 “first metal layer”, referring to FIGS. 1D-1G; patterning the solder mask 30 to form opening wherein a second metla layer 28 “plating layer” is formed, referring to FIG. 1H.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898