DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-25 and 42-46 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamano et al. (US 2009/0008765), (hereinafter, Yamano).
RE Claim 21, 42 and 50, Yamano discloses in FIGS. 1-46 a method of producing a chip embedded substrate. Yamano discloses a method of manufacturing an electronic device, the method comprising:
providing a signal distribution structure 405/408 on a first carrier 401 “support substrate” [0171 and 0186], referring to FIG. 5L, wherein the signal distribution structure 405/408 comprises a plurality of conductive layers 405/408 and a plurality of dielectric layers 406/406a, wherein providing the signal distribution structure 405/408 comprises:
forming, over the first carrier 401, a first conductive layer 405 of the plurality of conductive layers 405/408, referring to FIG. 5E;
forming a first dielectric layer 406 of the plurality of dielectric layers 406/406a over the first conductive layer 405 such that a bottom side of the first dielectric layer 406 is on a top side of the first conductive layer 405. Since an upper surface portion of the conductive layer 405, examiner will consider the dielectric layer 406 surface that is in direct contact with the upper surface portion of the conductive layer 405 a bottom side of the first dielectric layer 406, hence meeting the claimed limitation;
forming an opening 406A “via opening” through the first dielectric layer 406 to expose a top side the first conductive layer 405, referring to FIG. 5F [0179]; and
forming a second conductive layer 408 of the plurality of conductive layers 405/408 over a top side of the first dielectric layer 406 such that a bottom side of the second conductive layer is on a top side of the first dielectric layer 406 and such that the bottom side of the second conductive layer 408 extends vertically into the opening and onto the top side of the first conductive layer 405, referring to FIG. 5H;
coupling a bottom side of a semiconductor component 410 “semiconductor chip” to at least one or the plurality of conductive layers 405/408 of the signal distribution structure 405/408, referring to FIG. 5L [0187];
encapsulating lateral sides of the semiconductor component in an encapsulating material D1, referring to FIG. 5M [0190];
attaching a second carrier 501 to the encapsulating material D1, referring to FIG. 6B [0196-0198];
removing the first carrier 401 from the signal distribution structure 402/405/408, referring to FIG. 6C [0199]; and
providing interconnection structures 402 such that each interconnection structure 402 is coupled to at least one of the plurality of conductive layers 405/408 via a bottom side of the signal distribution structure 405/408; and exposing a top side of the encapsulating material 503, wherein the exposing the top side of the encapsulating material 503 comprises removing the second carrier 501.
RE Claims 22 and 43, Yamano discloses a method, wherein the forming the second conductive layer 408 comprises
forming a seed layer 407 “copper seed layer” of second conductive layer 408 such that a bottom side of the seed layer 407 contacts the top side of the first dielectric layer 406 and extends vertically into the opening 406A and contacts the top side of the first conductive layer 405, referring to FIG. 5G [0180].
RE Claims 23 and 44, Yamano discloses a method, wherein the coupling the bottom side of the semiconductor component 410 to at least one of the plurality of conductive layers 405/408 comprises coupling conductive bumps 411 “bumps” along the bottom side of the semiconductor component 410 to conductive pads 408b “pattern wiring” along a top side of the signal distribution structure 405/408. Examiner notes that the “pattern wiring” 408b is functionally equivalent to conductive pads.
RE Claims 24 and 45, Yamano discloses a method, comprising:
providing under bump metal 413 on the bottom side of the signal distribution structure 405/408; and
wherein the providing the interconnection structures 402 comprises providing the interconnection structures 402 on the under bump metal 413.
RE Claims 25 and 46, Yamano discloses a method, wherein the coupling the bottom side of the semiconductor component 410 comprises coupling the bottom side of the semiconductor component 410 to at least one of the plurality of conductive layers 405/408 via conductive attachment structures 409 “solder portions, referring to FIG. 5L [0185].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 26-28 and 47-49 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et al. (US 2009/0008765), (hereinafter, Yamano) in view of Kwon et al. (US 2016/0064328), (hereinafter, Kwon).
RE Claims 26 and 47, Yamano does not disclose a method, wherein the encapsulating the lateral sides of the semiconductor component 410 underfills the bottom side of the semiconductor component such that the encapsulating material encapsulates the conductive attachment structures.
However, in the same field of endeavor, Kwon discloses a method of making stacked silicon chips interconnect structure, wherein the encapsulating 117/116 the lateral sides of the semiconductor component 110 underfills the bottom side of the semiconductor component such that the encapsulating material encapsulates the conductive attachment structures 114 [0023]. Examiner notes that the underfill material 116 encapsulating the conductive attachment structures 114 is formed of a similar material as the epoxy-based encapsulant material 117 [0023], hence meeting the claimed limitation.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant case, to have the encapsulant D1 of Yamano disclosure to underfills the bottom side of the semiconductor component such that the encapsulating material encapsulates the conductive attachment structures in order to achieve one-step encapsulation process for a cost-effective 3D packaging process.
RE Claims 27, 28, 48 and 49, Yamano does not disclose a method, comprising providing an underfill material between the bottom side of the semiconductor component 410 and a top side of the signal distribution structure such that the underfill material encapsulates the conductive attachment structures.
However, in the same field of endeavor, Kwon discloses a method of making stacked silicon chips interconnect structure, comprising providing an underfill material 116 between the bottom side of the semiconductor component 110 and the top side of the signal distribution structure 102 "interposer" such that the underfill material 116 encapsulates the conductive attachment structures 114, hence meeting the claimed limitation of Claim 28.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant case, to have the encapsulant D1 of Yamano disclosure to underfills the bottom side of the semiconductor component such that the encapsulating material encapsulates the conductive attachment structures in order to achieve one-step encapsulation process for a cost-effective 3D packaging process.
Claim(s) 29 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamano et al. (US 2009/0008765), (hereinafter, Yamano) in view of HOU et al. (US 8,802,594), (hereinafter, HOU).
RE Claim 29, Yamano discloses a method, wherein removing the first carrier 401, referring to FIGS. 6C.
Yamano does not disclose a method, wherein the removing the first carrier comprises:
grinding away a first portion of the first carrier; and
etching away a second portion of the first carrier.
However, in the same field of endeavor, HOU discloses a method of forming a semiconductor device (10) comprises: forming a conductive pad (22) in a first substrate 20; forming an interconnecting structure (30) over the conductive pad and the first substrate, where the interconnecting structure comprises many metal layers disposed in many dielectric layers; bonding a die to a first side of the interconnecting structure; and etching the first substrate from a second side of the interconnecting structure, where the step of etching exposes a portion of the conductive pad; wherein the step of etching the first substrate 20 comprises: mounting a carrier to a backside surface of the die;
grinding a portion of the first substrate; and etching remaining portion of the first substrate to expose the conductive pad, referring to FIGS. 2D-2E [column 7, lines 66-67 and column 8, lines 1-45].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the two-step etching process similar to HOU’s disclosed removal process as a well-known substrate removal process in order to achieve precise selective carrier removal of Yamano’s disclosure.
Allowable Subject Matter
Claims 51 and 52 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to Claim(s) 21 and 42 have been considered but are not persuasive since exposing a top side of the encapsulating material 503, requires the removing of the second carrier 501, which is met by the prior art of record.
Therefore, the rejection of Claims 21 and 42 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, LIN et al. (2015/0145142) discloses a package structure and a method for forming a package structure are provided. The package structure includes a semiconductor die and a molding compound partially or completely encapsulating the semiconductor die. The package structure also includes a through package via in the molding compound. The package structure further includes an interfacial layer between the through package via and the molding compound. The interfacial layer includes an insulating material and is in direct contact with the molding compound.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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