CTFR 18/623,267 CTFR 97722 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered. Drawings In view of Applicant’s amendments, the prior drawing objection with respect to claim 2 is withdrawn. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a position of the first opening and a position of the second opening partially overlapping each other as found in claim 2; a third opening in the second resist mask, and simultaneous implantation from the second and third openings to form the anode layer and the termination well layer as found in claim 5; and a position of the first opening and a position of the second opening partially overlapping each other such that the position of the second opening extends outside the position of the first opening and such that the position of the first opening extends outside the position of the second opening as found in claim 7, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 In view of Applicant’s amendments, the prior 112(b) rejections are withdrawn. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (Re Claim 2) As a position of an opening is understood to be a point occupied by the opening, it is unclear how two positions – two points - could partially overlap each other. Furthermore, as the openings as shown in the figures are not present on the device at the same time, it is unclear how to interpret “overlap each other” as claimed. What is required by “a position of the first opening and a position of the second opening partially overlap each other” is therefore unclear. During examination, “a position of the first opening and a position of the second opening partially overlap each other” was understood to require that a third region of the first main surface, that is coextensive with where the first opening is formed, partially overlaps with a fourth region of the first main surface, that is coextensive with where the second opening is formed. (Re Claim 7) Similarly to the 112(b) rejection of claim 2 above, as a position of an opening is understood to be a point occupied by the opening, it is unclear how two positions – two points - could partially overlap each other, or have any extent. Furthermore, as the openings as shown in the figures are not present on the device at the same time, it is unclear how to interpret “overlap each other” as claimed. What is required by “a position of the first opening and a position of the second opening partially overlap each other such that the position of the second opening extends outside the position of the first opening and such that the position of the first opening extends outside the position of the second opening” is therefore unclear. During examination, “a position of the first opening and a position of the second opening partially overlap each other” was understood to require that a third region of the first main surface, that is coextensive with where the first opening is formed, partially overlaps with a fourth region of the first main surface, that is coextensive with where the second opening is formed, wherein an orthographic projection of the third region onto the first main surface extends outside the boundary of the fourth region, and an orthographic projection of the fourth region onto the first main surface extends outside the boundary of the third region. Claim Rejections - 35 USC § 103 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-21-aia AIA Claim s 1-3 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2016/0141400) referred to as Takahashi400, Nakamura (US 2018/0182844), Takahashi (US 2008/0048295) referred to as Takahashi295, Tanabe et al. (US 2018/0151557), Onishi et al. (US 2016/0233130), and Yoshida et al. (US 2017/0047322), all of record . (Re Claim 1) Takahashi400 teaches a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a semiconductor substrate (doped regions between 46 and 64; Fig. 11) of a first conductivity type (n-type; ¶30) having a first main surface (topmost contacting surface; Fig. 11) and including a first region (coextensive with the collector 62; Fig. 11) where an IGBT region (12; Fig. 11) is formed and a second region (coextensive with the cathode 70; Fig. 11) where a diode region (14; Fig. 11) is formed side by side in a first direction (left to right as seen in Fig. 11) along the first main surface; forming a carrier accumulation layer (44; Fig. 11); forming a base layer (42; Fig. 11) of a second conductivity type (p-type) between the first main surface and the carrier accumulation layer (Fig. 11); and forming an anode layer (32+200; Fig. 11, ¶55), and forming trenches (30h+30i+30j+30k; Fig. 11) at least in the second region, wherein the trenches in the second region extend deeper than the anode layer (all trenches extend deeper than the anode layer 32; Fig. 11) in a direction pointing from the first main surface to the second main surface (Fig. 11). Takahashi400 has not been shown to explicitly teach the method comprising the steps of: forming a first resist mask having a first opening on the first main surface of the semiconductor substrate at the first region; implanting impurity ions of a first conductivity type from the first opening to form the carrier accumulation layer of a first conductivity type; implanting impurity ions of a second conductivity type from the first opening to form the base layer of a second conductivity type between the first main surface and the carrier accumulation layer; forming a second resist mask having a second opening on the first main surface of the semiconductor substrate at the second region; and implanting impurity ions of a second conductivity type from the second opening to form the anode layer of a second conductivity type from a position deeper from the first main surface than a depth at which the carrier accumulation layer is formed to the first main surface. Takahashi295 teaches forming p-type doped regions for an IGBT and diode region using two separate steps (Fig. 33-34, ¶¶127-128). Tanabe teaches forming a carrier accumulation layer (18; Fig. 8) in an IGBT region (10; Fig. 8), and not within a diode region (20; Fig. 8), coextensive with a collector (14; Fig. 8). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the base layer 42 and the layer 32 of Takahashi400 using separate formation steps, as taught by Takahashi295, to allow for the p-type layer that is deposited within the diode region to be doped differently from the p-type layer that is deposited within the IGBT region of Takahashi400, thus suppressing hole injection and reducing the peak current during recovery (Takahashi295: ¶88). Furthermore, a PHOSITA would find it obvious to form the carrier accumulation layer such that it is in contact with an underside of the base layer of modified Takahashi400, but not also located within the diode region, as taught by Tanabe, in order to reduce hole injection from the IGBT region to the diode region of modified Takahashi400 (Tanabe: ¶70). Onishi teaches utilizing masks (60, 62, and 64; Fig. 5-7) formed on a first main surface (top surface; Fig. 5-7) of a semiconductor substrate (between 12a and 12b; Fig. 5-8) with openings formed according to the desired location and shape of doped regions that are formed using ion implantation through the masks (Fig. 5-7, ¶42-44); and counter-doping the region doped with 33a, and the p-type region 33, using impurity ions 35a (Fig. 4, ¶¶27, 40-41). As the anode layer 200 of Takahashi400 extends deeper into the semiconductor substrate than other doped regions, a PHOSITA would find it obvious to form the anode layer 200 using ion implantation through a second opening in a second mask, in the manner taught by Onishi (¶¶42-44), to take advantage of ion implantation’s good depth control and precise doping, where the second opening overlaps with the anode layer 200. Furthermore, a PHOSITA would find it obvious to situate the second mask on the first main surface of the second region, in order to provide physical support to the second mask (Onishi: Fig. 5-7). Additionally, a PHOSITA would find it obvious to compensate for the presence of impurity ions of a first conductivity type, as taught by Onishi (demonstrates counter-doping the region doped with 33a, and the p-type region 33, using impurity ions 35a; Fig. 4, ¶¶27, 40-41), to form a region having the desired relative p- or n-type doping. This then results in implanting impurity ions of a second conductivity type (p-type) from the second opening to form an anode layer (200; Fig. 11) from a position deeper from the first main surface than a depth at which the carrier accumulation is formed (200 is below the trenches; Fig. 1) to the first main surface (Fig. 1). Nakamura teaches forming a carrier accumulation layer (128; Fig. 5) and a p-type region (130; Fig. 5) within a semiconductor substrate (everything beneath 129; Fig. 5) using ion implantation (¶137). A PHOSITA would find it obvious to form the base layer 42 and carrier accumulation layer 18 (from Tanabe) of modified Takahashi400 using ion implantation as taught by Nakamura (¶137), to take advantage of ion implantation’s good depth control and precise doping; and a PHOSITA would find it obvious to perform the ion implantations forming the base layer and carrier accumulation layer of modified Takahashi400 in the continuous fashion taught by Nakamura at a step before forming trenches, as this avoids using a mask that may be misaligned during manufacturing to selectively deposit the impurity ions in between trenches either the base or carrier accumulation layers, thereby introducing doping defects. Furthermore, a PHOSITA would find it obvious to use ion implantation through a first opening in a first mask, in the manner taught by Onishi (¶¶42-44), to implant impurity ions that form carrier accumulation layer 18 from Tanabe in modified Takahashi400, such that the implantation breadth is coextensive with the breadth of collector 62 of Takahashi400, to form the carrier accumulation layer only within first region of modified Takahashi400, in the manner taught by Tanabe, to reduce hole injection from the IGBT region to the diode region of modified Takahashi400 (Tanabe: “a portion having the collector region 14 is referred to as the IGBT cell 10 and a portion having the cathode region 22 is referred to as the diode cell 20. “; “The charge accumulation layer 18 is provided to an IGBT cell 10 at a location adjacent to a first principal plane 50 a than a second defect layer 15 b and in contact with a base region 11.”, ¶69; see also ¶70). Yoshida teaches forming a mask (34; Fig. 15) used for ion implantation using a resist (¶87). A PHOSITA would find it obvious to form the first mask of modified Takahashi400 using resist as taught by Yoshida, as resist material is suitable for blocking impurity ions during implanting. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp ., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). Onishi also teaches forming implanting impurity ions using the same mask when the difference for each doped region is with respect to impurity type and depth (Fig. 3, ¶40). A PHOSITA would find it obvious to perform the implanting impurity ions step of a second conductivity type from the first opening of the first mask as used to form the carrier accumulation layer, in the manner taught by Onishi (Fig. 3, ¶40), to form the base layer of a second conductivity type between the first main surface and the carrier accumulation layer, as the implantation steps to form the base layer and the carrier accumulation layer of modified Takahashi400 are performed such that the impurity ions for the base and carrier accumulation layer are introduced coextensively (Nakamura: Fig. 5), and sharing a mask reduces the number of masking operations required to form the device. Modified Takahashi400 then teaches the method comprising the steps of: forming a first resist mask (according to Onishi and Yoshida; see above) having a first opening on the first main surface of the first region; implanting impurity ions of a first conductivity type (n-type) from the first opening (according to Onishi, Tanabe, and Nakamura; see above) to form the carrier accumulation layer (From Tanabe; see above) of a first conductivity type; implanting impurity ions of a second conductivity type (p-type) from the first opening (according to Onishi and Takahashi295; see above) to form the base layer of a second conductivity type between the first main surface and the carrier accumulation layer; forming a second resist mask (according to Onishi and Yoshida; see above) having a second opening on the first main surface of the second region; and implanting impurity ions of a second conductivity type from the second opening to form the anode layer (Takahashi400: 200) of a second conductivity type from a position deeper from the first main surface than a depth at which the carrier accumulation layer is formed to the first main surface (Takahashi400: Fig. 11). (Re Claim 2) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, wherein the first opening and the second opening partially overlap each other (the first opening is open over the first region, but not the second; and the second opening overlaps with the anode layer 200; Takahashi400: Fig. 11), and wherein the carrier accumulation layer and the anode layer are formed by implanting impurity ions to partially overlap each other (due to ion implantation through openings exposing overlapping regions). (Re Claim 3) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, but has not been shown to explicitly teach the method wherein the step of forming the anode layer is performed before the step of forming the carrier accumulation layer. Onishi teaches an order of ion implantations may be changed freely (¶58). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the anode layer before forming the carrier accumulation layer as when to perform the implantation is a matter of choice; Nagaoka is silent as to when and how the anode layer 70 is formed, but it must be formed sometime. The options are before, after, or simultaneously with forming the carrier accumulation layer. Onishi demonstrates that it is understood that ion implantation allows for free selection of when and where impurity ions are implanted to form doped layers (Onishi: ¶58). And the number of doped layers in the entire device is finite. As there are only a finite number of options for when the anode layer is formed with respect to when the carrier accumulation layer is formed, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try forming the anode layer before the step of forming the carrier accumulation layer, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.). See also In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results). (Re Claim 6) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, further comprising forming a cathode layer (70; Fig. 11) of the first conductivity type between the drift layer and the second main surface of the semiconductor device at the second region (Fig. 11), and forming a collector layer (62; Fig. 11) of the second conductivity type between the drift layer and the second main surface of the semiconductor device at the first region (Fig. 11), wherein the collector layer and the cathode layer are provided side by side in the first direction (Fig. 11). (Re Claim 7) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, wherein a position of the first opening and a position of the second opening partially overlap each other such that the position of the second opening extends outside the position of the first opening and such that the position of the first opening extends outside the position of the second opening (the first opening is open over the first region, but not the second; and the second opening overlaps only with the anode layer 200; Takahashi400: Fig. 11), wherein the carrier accumulation layer and the anode layer are formed by implanting impurity ions to partially overlap each other (due to ion implantation through openings exposing overlapping regions). (Re Claim 8) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, wherein the trenches in the second region include a first trench (30k; Fig. 11) that is closest to the first region and a plurality of second trenches (30h+30i+30k; Fig. 11) that are farther from the first region than the first trench, and wherein the first trench and the plurality of second trenches each penetrate the anode layer (“penetrate the anode layer” does not require the trenches to extend from the top of the anode layer to the bottom; Fig. 11). (Re Claim 9) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, further comprising forming an electrode (46; Fig. 11) on the first main surface that directly contacts the anode layer (Fig. 11) . 07-22-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2016/0141400) referred to as Takahashi400, Nakamura (US 2018/0182844), Takahashi (US 2008/0048295) referred to as Takahashi295, Tanabe et al. (US 2018/0151557), Onishi et al. (US 2016/0233130), and Yoshida et al. (US 2017/0047322) as applied to claim 3 above, and further in view of Ma (US 2017/0352723), all of record . (Re Claim 4) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 3, but has not been shown to explicitly teach the method further comprising a heating step of diffusing impurity ions of the anode layer into the semiconductor substrate after the step of forming the anode layer, and wherein the step of forming the carrier accumulation layer is performed after the heating step. Onishi teaches a heating step of diffusing impurity ions after implantation (¶45). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to perform a heating step of diffusing impurity ions of the anode layer into the semiconductor substrate after the step of forming the anode layer, in order to activate the impurity ions (Onishi: ¶45). Ma teaches separately activating layers implanted with impurity ions. A PHOSITA would find it obvious to perform an individual heating step of diffusing impurity ions of the anode layer into the semiconductor substrate immediately after implanting, and so before forming the carrier accumulation layer, as taught by Ma, to reduce the total heat exposure of other implanted layers that have a smaller thermal budget. And performing a heating step of diffusing impurity ions of the anode layer immediately after implantation, as taught by Ma, predictably activates the anode layer. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004) . 07-22-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2016/0141400) referred to as Takahashi400, Nakamura (US 2018/0182844), Takahashi (US 2008/0048295) referred to as Takahashi295, Tanabe et al. (US 2018/0151557), Onishi et al. (US 2016/0233130), and Yoshida et al. (US 2017/0047322) as applied to claim 1 above, and further in view of Arakawa et al. (US 2019/0096878), all of record . (Re Claim 5) Modified Takahashi400 teaches the method for manufacturing a semiconductor device according to claim 1, but has not been shown to explicitly teach the method wherein the semiconductor substrate includes a third region in which a termination region is formed around the first region and the second region, wherein in the second resist mask, a third opening is formed on a first main surface of the third region, and wherein the step of forming the anode layer includes implanting impurity ions of the second conductivity type simultaneously from the second opening and the third opening to form the anode layer and the termination well layer of the second conductivity type. Arakawa teaches forming a termination region (from the outermost side of p-type layer 11 to the edges of the device 100; Fig. 1 and 2) around a device region (¶33). A PHOSITA would find it obvious to alternately form the first and second regions of modified Takahashi400, in correspondence with the alternate formation of the regions 10 and 20 taught by Arakawa, to form an RC-IGBT device capable of handling greater current through the formation of parallel device structures. See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.). A PHOSITA would also find it obvious then to utilize the structure of the termination region around the alternately formed first and second regions of modified Takahashi400, as taught by Arakawa, to increase the breakdown voltage of the semiconductor device (Arakawa: ¶34). Arakawa also teaches that the guard rings have a high impurity concentration (¶52), where the ring 30 at least has a higher impurity concentration than a base layer 11 (¶39), and is formed deeper than the base layer (Fig. 2, ¶39). Onishi teaches utilizing masks (60, 62, and 64; Fig. 5-7) formed on a first main surface (top surface; Fig. 5-7) of a semiconductor substrate (between 12a and 12b; Fig. 5-8) with openings formed according to the desired location and shape of doped regions that are formed using ion implantation through the masks (¶42-44). Koyama teaches simultaneously forming an anode layer (60; Fig. 24C, ¶193) and a termination well layer (“outer peripheral voltage withstand portion”; ¶193). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to simultaneously form the guard rings of modified Takahashi400 when forming the anode layer as both doped regions are of a higher concentration and are formed deeper than the base layer, and simultaneous ion implantation of these regions reduces the overall number of masking steps required. A PHOSITA would then find it obvious to form a third opening in the second resist mask used to form the anode layer of modified Takahashi400 that corresponds to the location of the guard rings of modified Takahashi400, in order to implant impurity ions to form the guard rings while simultaneously forming the anode layer, as simultaneous ion implantation of these regions reduces the overall number of masking steps required . Response to Arguments 07-37 AIA Applicant's arguments filed 2/24/2026 have been fully considered but they are not persuasive. Objections: Claim 5: Though Applicant appears to have support for the new flowchart, Fig. 26 omits a structure showing “in the second resist mask, a third opening is formed on a first main surface of the third region” and “wherein the step of forming the anode layer includes implanting impurity ions of the second conductivity type simultaneously from the second opening and the third opening to form the anode layer and a termination well layer of the second conductivity type”. Actual features are represented at least by “wherein in the second resist mask, a third opening is formed on a first main surface of the third region…simultaneously from the second opening and the third opening” as found in the claim. The drawing in a nonprovisional application must show every feature of the invention specified in the claims (37 C.F.R. 1.83). The remainder of Applicant’s arguments are moot in view of the new rejection . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Naito (US 2016/0336404) teaches that trench depth affects IE effects and collector-gate capacitance (¶85). Gejo (US 2016/0218101) teaches that a deeper anode layer in a diode region than a base layer in an IGBT region allows for breakdown to occur in the diode region before the IGBT region (Fig. 4, ¶¶37-39) . Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898 Application/Control Number: 18/623,267 Page 2 Art Unit: 2898 Application/Control Number: 18/623,267 Page 3 Art Unit: 2898 Application/Control Number: 18/623,267 Page 4 Art Unit: 2898 Application/Control Number: 18/623,267 Page 5 Art Unit: 2898 Application/Control Number: 18/623,267 Page 6 Art Unit: 2898 Application/Control Number: 18/623,267 Page 7 Art Unit: 2898 Application/Control Number: 18/623,267 Page 8 Art Unit: 2898 Application/Control Number: 18/623,267 Page 9 Art Unit: 2898 Application/Control Number: 18/623,267 Page 10 Art Unit: 2898 Application/Control Number: 18/623,267 Page 11 Art Unit: 2898 Application/Control Number: 18/623,267 Page 12 Art Unit: 2898 Application/Control Number: 18/623,267 Page 13 Art Unit: 2898 Application/Control Number: 18/623,267 Page 14 Art Unit: 2898 Application/Control Number: 18/623,267 Page 15 Art Unit: 2898 Application/Control Number: 18/623,267 Page 16 Art Unit: 2898 Application/Control Number: 18/623,267 Page 17 Art Unit: 2898 Application/Control Number: 18/623,267 Page 18 Art Unit: 2898
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