CTNF 18/623,293 CTNF 77022 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “the through via, the through via is connected to the second semiconductor chip, and the wiring layer is below the through via” renders the claim indefinite because the figure 1 shown the wiring layer (130) is above the through via. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 13-14 and 18-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Karhade et al [US 11,328,937]) IDS . With respect to claim 13, Karhade et al (fig. 2A) disclose a semiconductor package comprising: a first semiconductor chip (210, col. 3, lines 5-17); a second semiconductor chip (230, col. 3, lines 35-49) on the first semiconductor chip; and a molding layer (236, col. 4, lines 4-28) on the first semiconductor chip and on a side of the second semiconductor chip, wherein the second semiconductor chip includes a first portion that overlaps the molding layer, and an upper surface of the molding layer (236, col. 4, lines 4-28) is lower than an upper surface of the second semiconductor chip (230, col. 3, lines 35-49). With respect to claim 14, Karhade et al (fig. 2A) disclose wherein the upper surface of the molding layer (236, col. 4, lines 4-28) is curved. With respect to claim 18, Karhade et al (fig. 2A) disclose further comprising at least one external connection bump (238, col. 3, lines 25-31) on a lower surface of the first semiconductor chip and electrically connected to the first semiconductor chip. With respect to claim 19, Karhade et al (fig. 2A) disclose further comprising an underfill (236, col. 4, lines 4-28) on the first semiconductor chip and in a region below the second semiconductor chip. ** Notice : as interpreting the claim in a broad scope, the underfill can also be the same as the molding layer because the claims do not recite the material different between the underfill and the molding layer. With respect to claim 20, Karhade et al (fig. 2A) disclose wherein a width of the first semiconductor chip (210, col. 3, lines 5-17) is greater than a width of the second semiconductor chip (230, col. 3, lines 35-49) . 07-15 AIA Claim s 13-14 and 18-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by TERUJI [CN 101145545]) . With respect to claim 13, TERUJI (fig. 1) discloses a semiconductor package comprising: a first semiconductor chip (101); a second semiconductor chip (103) on the first semiconductor chip; and a molding layer (107) on the first semiconductor chip and on a side of the second semiconductor chip, wherein the second semiconductor chip includes a first portion that overlaps the molding layer, and an upper surface of the molding layer (107) is lower than an upper surface of the second semiconductor chip (103). With respect to claim 17, TERUJI (fig. 1) discloses wherein silicon is on the upper surface of the second semiconductor chip (103). With respect to claim 18, , TERUJI (fig. 1) discloses further comprising at least one external connection bump (111) on a lower surface of the first semiconductor chip (101) and electrically connected to the first semiconductor chip (103). With respect to claim 19, TERUJI (fig. 1) discloses further comprising an underfill (105) on the first semiconductor chip and in a region below the second semiconductor chip. With respect to claim 20, TERUJI (fig. 1) discloses wherein a width of the first semiconductor chip (101) is greater than a width of the second semiconductor chip (103) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3-4, 7, 10, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over TERUJI [CN 101145545]) . With respect to claims 3 and 15, TERUJI (fig. 1) discloses a semiconductor package comprising: a first semiconductor chip (101); a second semiconductor chip (103) on the first semiconductor chip; and a molding layer (107) on the first semiconductor chip and on a side of the second semiconductor chip, wherein an upper surface of the second semiconductor chip is above an upper surface of the molding layer. TERUJI does not mention the upper surface of the second semiconductor chip is above an upper surface of the molding layer by 0.3µm to 2.0µm. However, the height range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller , 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff , 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). With respect to claim 4, TERUJI (fig. 1) discloses wherein a side of the molding layer (107) is on a same plane as a side of the first semiconductor chip (101). With respect to claim 7, TERUJI (fig. 1) discloses further comprising an underfill (105) on the first semiconductor chip (101) and in a region below the second semiconductor chip (103). With respect to claim 10, TERUJI (fig. 1) discloses further wherein the upper surface of the molding layer (107) is planar. With respect to claim 12, TERUJI (fig. 1) discloses wherein a width of the first semiconductor chip (101) is greater than a width of the second semiconductor chip (103) . 07-21-aia AIA Claim s 3-4, and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade et al [US 11,328,937]) IDS . With respect to claim 3, Karhade et al (fig. 2A) disclose a semiconductor package comprising: a first semiconductor chip (210, col. 3, lines 5-17); a second semiconductor chip (230, col. 3, lines 35-49) on the first semiconductor chip; and a molding layer (236, col. 4, lines 4-28) on the first semiconductor chip and on a side of the second semiconductor chip, wherein an upper surface of the second semiconductor chip is above an upper surface of the molding layer. Karhade et al do not mention the upper surface of the second semiconductor chip is above an upper surface of the molding layer by 0.3µm to 2.0µm. However, the height range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller , 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff , 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). With respect to claim 4, Karhade et al (fig. 2A) disclose wherein a side of the molding layer (236, col. 4, lines 4-28) is on a same plane as a side of the first semiconductor chip (210, col. 3, lines 5-17). With respect to claim 7, Karhade et al (fig. 2A) disclose further comprising an underfill (236, col. 4, lines 4-28) on the first semiconductor chip and in a region below the second semiconductor chip. **Notice: as interpreting the claim in a broad scope, the underfill can also be the same as the molding layer because the claims do not recite the material different between the underfill and the molding layer. With respect to claim 8, Karhade et al (fig. 2A) disclose wherein the first semiconductor chip includes a through via (226, col. 3, lines 18-31) and a wiring layer (224, col. 3, lines 32-37) connected to the through via, the wiring layer faces the second semiconductor chip, and the through via is below the wiring layer. With respect to claim 9, Karhade et al (fig. 2A) disclose wherein the first semiconductor chip includes a through via (226, col. 3, lines 18-31) and a wiring layer (224, col. 3, lines 32-37) connected to the through via, the through via is connected to the second semiconductor chip, and the wiring layer is below the second semiconductor chip. With respect to claim 10, Karhade et al (fig. 2A) disclose further wherein the upper surface of the molding layer (236, col. 4, lines 4-28) is planar. With respect to claim 11, Karhade et al do not mention wherein a height of the upper surface of the molding layer is variable with respect to the upper surface of the first semiconductor chip in an area between the side of the second semiconductor chip and a side of the molding layer. However, the height range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). With respect to claim 12, Karhade et al (fig. 2A) disclose wherein a width of the first semiconductor chip (210, col. 3, lines 5-17) is greater than a width of the second semiconductor chip (230, col. 3, lines 35-49) . . 07-21-aia AIA Claim s 1, 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over TERUJI [CN 101145545]) in view of Chiu et al [US 2022/0319945] . TERUJI (fig. 1) discloses a semiconductor package comprising: a first semiconductor chip (101); a second semiconductor chip (103) on the first semiconductor chip; at least one connection bump (109) between the first semiconductor chip and the second semiconductor chip; an underfill (105) in a region below the second semiconductor chip and on a side of the at least one connection bump; and a molding layer (107) on the first semiconductor chip and on a side of the second semiconductor chip, wherein an upper surface of the second semiconductor chip (103) is above an upper surface of the molding layer (107), a height difference between the upper surface of the second semiconductor chip and the upper surface of the molding layer. TERUJI does not mention the upper surface of the second semiconductor chip is above an upper surface of the molding layer by 0.3µm to 2.0µm. However, the height range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller , 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff , 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). TERUJI does not mention a surface roughness of the upper surface of the second semiconductor chip is 3nm or less. However, Chiu et al (fig. 1) disclose surface roughness of the upper surface of the second semiconductor chip (12, 14, pp. [0064]). Moreover, the roughness range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Therefore, it would have been obvious to one skill in the art to have the roughness of the upper surface of the semiconductor chip as taught by Chiu et al in view of TERUJI in order to provide the known purpose of improving the adhesive between the semiconductor chip and other device . 07-22-aia AIA Claim s 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over TERUJI [CN 101145545]) in view of Chiu et al [US 2022/0319945] as applied to claim s 1 and 3 above, and further in view of Liu et al [US 2024/0047436] . TERUJI does not mention wherein each of the first semiconductor chip and the second semiconductor chip is a logic chip. However, Liu et al (fig. 1K) disclose wherein each of the first semiconductor chip (130, pp [0035]) and the second semiconductor chip (170, pp [0035]) is a logic chip. Therefore, it would have been obvious to one skill in the art to have the logic chip as taught by Liu et al into the device of TERUJI in order to provide suitable design function for a semiconductor device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 571-271-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HOAI V PHAM/Primary Examiner, Art Unit 2892 Application/Control Number: 18/623,293 Page 2 Art Unit: 2892 Application/Control Number: 18/623,293 Page 3 Art Unit: 2892 Application/Control Number: 18/623,293 Page 4 Art Unit: 2892 Application/Control Number: 18/623,293 Page 5 Art Unit: 2892 Application/Control Number: 18/623,293 Page 6 Art Unit: 2892 Application/Control Number: 18/623,293 Page 7 Art Unit: 2892 Application/Control Number: 18/623,293 Page 8 Art Unit: 2892 Application/Control Number: 18/623,293 Page 9 Art Unit: 2892 Application/Control Number: 18/623,293 Page 10 Art Unit: 2892 Application/Control Number: 18/623,293 Page 12 Art Unit: 2892
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