Prosecution Insights
Last updated: August 17, 2026
Application No. 18/623,316

IMAGE SENSING DEVICE INCLUDING SOURCE FOLLOWER TRANSISTOR

Non-Final OA §102
Filed
Apr 01, 2024
Priority
Sep 14, 2023 — RE 10-2023-0122368
Examiner
HENRY, CALEB E
Art Unit
Tech Center
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1087 granted / 1253 resolved
+26.8% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
1288
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
55.4%
+15.4% vs TC avg
§102
34.5%
-5.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1253 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 9-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin (20220406825). Regarding claim 1, Jin teaches a image sensing device (fig. 5 and 6) comprising: a semiconductor substrate (fig. 5 and 6: 100) configured to include a first surface upon which light is incident from a scene and a second surface facing or opposite to the first surface; first (fig. 6: please see 110a-d) and second (fig. 6: please see 110a-d) photoelectric conversion elements that are supported by the semiconductor substrate and are spaced apart from each other, each photoelectric conversion element configured to receive incident light and generate photocharges by sensing the received incident light; a first pixel isolation structure (fig. 6: please see the multiple PIS segments) recessed from the second surface and configured to surround the first and second photoelectric conversion elements; second (fig. 6: please see the multiple PIS segments) and third (fig. 6: please see the multiple PIS segments) pixel isolation structures disposed between the first photoelectric conversion element and the second photoelectric conversion element and spaced apart from each other; and a source follower transistor (SF; par. 74 teaches PTR includes SF) supported by the semiconductor substrate and configured to include a gate (PG) disposed on the second surface in at least a portion of a gap region between the second pixel isolation structure and the third pixel isolation structure. Regarding claim 2, Jin teaches a image sensing device according to claim 1, wherein: the gate of the source follower transistor is disposed to overlap at least one of the first and second photoelectric conversion elements (please see fig. 6). Regarding claim 3, Jin teaches a image sensing device according to claim 1, wherein: each of the second pixel isolation structure and the third pixel isolation structure is in contact with the first pixel isolation structure (all elements seen in fig. 5 and 6 are in close proximity or association, i.e. contact, with each other). Regarding claim 4, Jin teaches a image sensing device according to claim 1, further comprising: a fourth pixel isolation structure disposed in the gap region (please see fig. 6 which show multiple portions of PIS). Regarding claim 5, Jin teaches a image sensing device according to claim 1, further comprising: a first floating diffusion region (please see multiple FDs in fig. 5 and 6) configured to store photocharges that are generated by the first photoelectric conversion element in response to the incident light; and a second floating diffusion region (please see multiple FDs in fig. 5 and 6) configured to store photocharges that are generated by the second photoelectric conversion element in response to the incident light. Regarding claim 6, Jin teaches a image sensing device according to claim 5, further comprising: a first transfer transistor (please see multiple PTR in fig. 5 and 6) having a first terminal electrically connected to the first photoelectric conversion element and a second terminal electrically connected to the first floating diffusion region; and a second transfer transistor (please see multiple PTR in fig. 5 and 6) having a first terminal electrically connected to the second photoelectric conversion element and a second terminal electrically connected to the second floating diffusion region (please see fig. 5 and 6). Regarding claim 7, Jin teaches a image sensing device according to claim 6, wherein: the gate of the first transfer transistor overlaps the first photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor (please see fig. 5 and 6); and the gate of the second transfer transistor overlaps the second photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor (please see fig. 5 and 6). Regarding claim 9, Jin teaches a image sensing device according to claim 5, further comprising: a reset transistor (par. 74) supported by the semiconductor substrate and structured to include a gate that overlaps the first photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, wherein the reset transistor is configured to drain photocharges stored in the first and the second floating diffusion regions (please see fig. 5 and 6). Regarding claim 10, Jin teaches a image sensing device according to claim 1, further comprising: a selection transistor (par. 74) supported by the semiconductor substrate and structured to include a gate that overlaps the second photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, wherein the selection transistor outputs an electrical signal having a voltage level corresponding to the photocharges generated by the first or second photoelectric conversion element (please see fig. 5 and 6). Regarding claim 11, Jin teaches a image sensing device according to claim 1, further comprising: a drain transistor (par. 74) supported by the semiconductor substrate and structured to include a gate that overlaps the first photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from a gate of the source follower transistor, wherein the photocharges generated by the first or second photoelectric conversion element are reset by the drain transistor (please see fig. 5 and 6; par. 74). Regarding claim 12, Jin teaches a image sensing device according to claim 6, further comprising: a dual conversion gain (DCG) transistor (DCX; par. 74) supported by the semiconductor substrate and structured to include a gate that overlaps the first photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, wherein the DCG transistor changes a capacitance of at least one of the first and the second floating diffusion regions (please see fig. 5 and 6; par. 74). Regarding claim 13, Jin teaches a image sensing device according to claim 5, further including: a metal interconnect layer (ML) configured to contact each of the first floating diffusion region and the second floating diffusion region while being located outside the semiconductor substrate, wherein the metal interconnect layer electrically connects the first floating diffusion region and the second floating diffusion region to each other (please see fig. 5 and 6). Regarding claim 14, Jin teaches a image sensing device comprising: a semiconductor substrate (fig. 5 and 6: 100) configured to include a first surface upon which light is incident and a second surface facing or opposite to the first surface; a first photoelectric conversion element (fig. 6: please see 110a-d) supported by the semiconductor substrate and configured to generate photocharges in response to the incident light; a second photoelectric conversion element (fig. 6: please see 110a-d) supported by the semiconductor substrate and spaced apart from the first photoelectric conversion element, and configured to generate photocharges in response to the incident light; and a source follower transistor ((SF; par. 74 teaches PTR includes SF) supported by the semiconductor substrate and structured to include a gate (PG) disposed in a gap region between the first photoelectric conversion element and the second photoelectric conversion element, wherein the gate of the source follower transistor overlaps at least a portion of each of the first photoelectric conversion element and the second photoelectric conversion element that are arranged in a first direction perpendicular to the second surface. Regarding claim 15, Jin teaches a image sensing device according to claim 14, further comprising: a first transfer transistor (please see multiple PTR in fig. 5 and 6) supported by the semiconductor substrate and structured to include a gat that overlaps the first photoelectric conversion element in the first direction and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor; and a second transfer transistor supported by the semiconductor substrate and structured to include a gate that overlaps the second photoelectric conversion element in the first direction and is disposed on the second surface of the semiconductor substrate to be spaced apart from both the gate of the source follower transistor and the gate of the first transfer transistor (please see fig. 5 and 6). Regarding claim 16, Jin teaches a image sensing device according to claim 15, further comprising: a floating diffusion region (please see multiple FDs) supported by the semiconductor substrate within a space between the gate of the first transfer transistor and the gate of the second transfer transistor, and arranged adjacent to the second surface of the semiconductor substrate (please see fig. 5 and 6). Regarding claim 17, Jin teaches a image sensing device according to claim 15, further comprising: a first floating diffusion region (please see multiple FDs) spaced apart from the gate of the first transfer transistor, disposed within the semiconductor substrate, and adjacent to the second surface; and a second floating diffusion region spaced apart from the gate of the second transfer transistor, disposed within the semiconductor substrate, and adjacent to the second surface (please see fig. 5 and 6). Regarding claim 18, Jin teaches a image sensing device according to claim 17, further comprising: a metal interconnect layer (ML) configured to contact each of the first floating diffusion region and the second floating diffusion region while being located outside the semiconductor substrate, wherein the metal interconnect layer electrically connects the first floating diffusion region and the second floating diffusion region to each other (please see fig. 5 and 6). Regarding claim 19, Jin teaches a image sensing device according to claim 14, further comprising: a pixel isolation structure recessed from the first surface of the semiconductor substrate corresponding to the gap region toward an inside of the semiconductor substrate (please see multiple portions of PIS in fig. 6). Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Apr 01, 2024
Application Filed
Jul 14, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+6.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1253 resolved cases by this examiner. Grant probability derived from career allowance rate.

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