DETAILED ACTION
This action is responsive to the following communication: the response filed 6/4/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group 1 (claims 1-5) in the reply filed on 6/4/26 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirose et al. (US 2016/0005475 “Hirose”) in view of Lee et al. (US 6,166,961 “Lee”).
Regarding claim 1, Hirose discloses a semiconductor device comprising:
a memory cell (fig. 2A, 2B) connected to a first line (BL; fig. 2A, 2B) and a second line (WLS/WL; fig. 2A, 2B);
at least one of first (voltage pumps 320, 300; fig. 1) each configured to provide (“VPOS and VNEG voltages are independently generated by a pair of voltage pump circuits (320, 330)” para 0042) a first input voltage (VPOS/VNEG for erase/program; fig. 4) of a first node (BL terminal node; fig. 2A, 2B) to the first line (BL); and
at least one of second (voltage pumps 320, 300; fig. 1) each configured to provide (“VPOS and VNEG voltages are independently generated by a pair of voltage pump circuits (320, 330)” para 0042) a second input voltage (VNEG/VWL/VPOS for erase/program; fig. 4) of a second node (WL terminal node; fig. 2A, 2B) to the second line (WLS/WL),
wherein the first and second nodes are provided with the first and second input voltages having different polarities (one of a positive polarity and one of a negative polarity corresponding to erase/program operations; fig. 4, para 0042-0043),
wherein the polarities (i.e. positive, negative polarities) of the first and second input voltages that are provided to the first and second nodes are determined based on data to be written (i.e. data “1” written for program, data “0” written for erase) in the memory cell (“a “1” bit may be stored within the memory cell by raising the threshold voltage of a programmed SONOS transistor to a substantially positive (or alternatively, a slightly negative) Vt … an erased SONOS transistor with a substantially negative Vt may be used to store a “0” bit within the memory cell” para 0031), and
and a back bias voltage (a P-Well bias; fig. 3) is adjusted (i.e. to be a positive VPOS or a negative VNEG voltage corresponding to erase/program operations; fig. 4) in response to a change in the polarity of each of the first and second input voltages (i.e. based on whether the input voltages changes to positive, negative polarities, the P-Well bias is adjusted to VPOS or VNEG accordingly; fig. 4).
Hirose does not expressly disclose first transistors, second transistors, and wherein at least one of a voltage of each of control terminals of the first and second transistors and a back bias voltage of each of the first and second transistors.
Lee discloses first transistors (Q1-Q8 corresponding to voltage pumps circuits 12, 13; fig. 3, 4a), second transistors (Q11-Q18 corresponding to voltage pumps circuits 12, 13; fig. 3, 4b), and wherein at least one of a voltage (Vnn, Vss; fig. 4a, 4b) of each of control terminals (i.e. gate terminals) of the first and second transistors and a back bias voltage (i.e. P-well, N-well bias) of each of the first and second transistors is adjusted (i.e. via a switching circuit; column/line(s): 4/27+).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hirose is modifiable as taught by Lee for the purpose of utilizing voltage pumps that provides particular biases, to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (column/line(s): 1/43+ of Lee).
Allowable Subject Matter
Claim(s) 2-5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record and is considered pertinent to applicant’s disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 2 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely a first positive voltage is applied to each of the control terminals of the second transistors and a negative voltage is provided as a back bias voltage of each of the second transistors, and a second positive voltage is applied to each of the control terminals of the first transistors and a ground voltage is provided as a back bias voltage of each of the first transistors, the second positive voltage being higher than the first positive voltage..
With respect to dependent claim 4 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely global column transistor has a first terminal connected to the first node and a second terminal connected to the local column transistor, and the local column transistor has a first terminal connected to the second terminal of the global column transistor and a second terminal connected to the bit line, and wherein the global row transistor has a first terminal connected to the second node and a second terminal connected to the local row transistor, and the local row transistor has a first terminal connected to the second terminal of the global row transistor and a second terminal connected to the word line.
The allowable claims are supported in at least fig. 1 of the instant application.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Otsuka (US 2010/0265757), teaches a resistance change memory device which can be readily reduced in voltage when voltages of opposite polarity are applied to the storage element during data write and erase operations.
Widjaja (US 2017/0229178), teaches resistivity state of a bipolar resistive memory element depends on the polarity of the potential difference or current flow across the bipolar resistive memory element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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