DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II, directed to claims 1-3, 5-10, and 14-17 in the reply filed on 08/25/2026 is acknowledged.
Claims 4, 11-13, and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/25/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3: The claim language “in-situ etching” is indefinite. The specification does not clarify the location and/or processes that are performed “in-situ”, this could mean within the same processing chamber, or alternatively, within the same apparatus with multiple processing chambers. It is also indefinite with regards to what process is being performed “in-situ”, this could mean just etching within a processing chamber, or alternatively, etching combined with some other manufacturing process within the same processing chamber. For the purposes of examination, “in-situ etching” will be interpreted as etching within a processing chamber.
Regarding claim 8: The possible materials of the sacrificial layer and the protection layer both include AlGaN, however the etching selectivity ratio of the sacrificial layer to the protection layer is also stated to be less than 1. It is unclear based on the claim language if both the sacrificial layer and the protection layer can be AlGaN, or alternatively, if the sacrificial layer and the protection layer must be different materials. If AlGaN can be selected for each layer, it is not clear how these can have a different etch selectivity. For the purposes of examination, it will be assumed that the sacrificial layer and the protection layer must be different materials. The claim language must require selection of different materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-7, 10, 14-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20150048421 A1), hereinafter referred to as Park421, in view of Khan et al. (US 20100187545 A1) hereinafter referred to as Khan545.
Regarding claim 1: Park421 teaches a method for manufacturing a semiconductor structure, comprising: sequentially stacking a substrate (See at least Fig. 2, SUB10), a heterojunction structure layer (See at least Fig. 2, C10 and CS10), and a P-type semiconductor layer (See Fig. 2 PL10’); remaining the P-type semiconductor layer in a gate region and etching the P-type semiconductor layer in a non-gate region (See Fig. 2, “After forming the gate electrode G10, the second regions R20 (see FIG. 1) at opposite sides of the gate electrode G10 and the first region R10 are etched to a desired or alternatively predetermined thickness”, para. [0086]); Park421 teaches that the p-type impurities of the P-type layer may be magnesium (“the p-type impurities may include magnesium (Mg)”, para. [0077]) and that the surface of the of the P-type layer has a concertation that is less than a preset value to form a high-resistance region (“a hole concentration of the second region R20 may be about 5.times.10.sup.16/cm.sup.3 or less.”, para. [0078], in light of the specification, the preset value is interpreted as 1.times.10.sup.15/cm.sup.3).
Park421 does not teach the doping method of: growing a sacrificial layer on the P-type semiconductor layer, and magnesium ions on a surface of the P-type semiconductor layer diffusing into the sacrificial layer; etching the sacrificial layer; and repeating N times processes of growing the sacrificial layer on the P-type semiconductor layer first and then etching the sacrificial layer.
Khan545 teaches a method of growing a sacrificial layer (“a dielectric layer (18) is grown over the group III nitride epilayer (12), such as shown in FIG. 2.”, para. [0046]), diffusing into the sacrificial layer (“The dielectric layer (18) overlying the group III nitride epilayer (12) in selected areas, such as shown in FIG. 6, is subjected to an annealing process”, para. [0070], at the annealing temperatures taught by Khan545 of 300 C to 1200 C dopants will necessarily diffuse into the sacrificial layer) and removing the sacrificial layer by etching (“The excess dielectric layer (18) overlying the doped regions (24) of the group III nitride epilayer (12) can then be removed via etching”, para. [0074]). Khan545 teaches that this process may be repeated any number of times (“No matter which of the above processes are utilized to produce the selectively doped substrate, the process can be repeated any number of times to produce a substrate having the desired characteristics.”, para. [0082]) and that the dopant may be magnesium (“the p-type layer (68) can be selectively doped with magnesium”, para. [104]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the desired dopant concentration profile could be obtained by growing a sacrificial layer, diffusing dopants into the sacrificial layer, then removing the sacrificial layer, repeating the process as many times as needed as taught by Khan545. A person of ordinary skill in the art would recognize this method can improve the level of control of the amount of doping in the P-type layer (See Khan545, “Thus, by controlling of the conductivity of the group III nitride epilayer in select areas of the epilayer, the overall performance of the epilayer can be selectively controlled.”, para. [0035]). A person of ordinary skill in the art could have substituted the doping method of Khan545 into the method taught by Park421 to arrive at the claimed invention, and the results of this combination would be predictable.
PNG
media_image1.png
373
761
media_image1.png
Greyscale
Fig. 2 taken from Park421 and annotated: P-type layer P10’ is etched in the non-gate region, concentration of p-type impurities is lower in regions R20’.
Regarding claim 2: In addition to the reasoning used to reject claim 1, Park421 teaches providing a source electrode (S10’) on the heterojunction structure layer in a source region, providing a drain electrode (D10’) on the heterojunction structure layer in a drain region, and providing a gate electrode (G10) in the gate region (See Fig. 2 annotated below).
Regarding claim 5: The method of Park421 and Khan545 teach the method for manufacturing the semiconductor structure according to claim 1, wherein the sacrificial layer is a non-intentionally doped layer. (The examiner interprets “non-intentionally doped” to mean that some dopants diffuse from the P-type layer into the sacrificial layer; at the annealing temperatures taught by Khan545, impurities will necessarily diffuse into the sacrificial layer).
Regarding claim 6: In addition to the reasoning used to reject claim 1, Park421 does not teach after remaining the P-type semiconductor layer in the gate region and etching- the P-type semiconductor layer in the non-gate region, conformally providing a protection layer on the P-type semiconductor layer.
Khan545 teaches conformally providing a protection layer (Photo-resist 20) on the P-type semiconductor layer (“The method includes depositing a photo-resist layer directly on an epilayer of a substrate.”, para. [0011], see Fig. 12).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that a protection layer could be used to control the location and concentration of dopants diffused by the sacrificial layer into the P-type layer. A person of ordinary skill in the art could use the teachings of Khan545 to include a protective layer conformally over the P-type layer of the device disclosed in Park421, modifying it to arrive at the claimed invention. The material of the P-type layer in Park421 (“GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN” para. [0077]) which includes the materials taught by Khan545 (“The group III nitride epilayer can be composed of any combination of group III elements (e.g., Al, In, and Ga) and nitride”, para. [0038]” so such a modification could be made with a reasonable expectation of success.
Regarding claim 7: In addition to the reasoning used to reject claim 6, Khan545 teaches that a material of the sacrificial layer (dielectric 18) is different from a material of the protection layer (photoresist 20), (“The photo-resist coating (20) can generally be composed of three basic elements: a base or resin, a solvent, and a polymer.”, para. [0060], “the dielectric layer is formed from silicon oxide or a silicon nitride”, para. [0047]).
Regarding claim 10: In addition to the reasoning used to reject claim 7, Khan545 teaches the material of the protection layer (photo-resist 20) is different from a material of the P-type semiconductor layer (group III nitride epilayer 12) (“e.g., AlGaN and AlInGaN”, para. [0037]).
Regarding claim 14: In addition to the reasoning used to reject claim 1, Park421 teaches a concentration of magnesium ions inside the P-type semiconductor layer is greater than 1E17/cm3. (“a hole concentration of the first region R10 may be about 5.times.10.sup.16/cm.sup.3 to about 1.times.10.sup.23/cm.sup.3”, para. [0078], the hole concentration is approximately equal to the p-type doping concentration).
Regarding claim 15: In addition to the reasoning used to reject claim 1, Park421 teaches a concentration of magnesium ions located in the high-resistance region is less than 1E15/cm3. (“a hole concentration of the second region R20 may be about 5.times.10.sup.16/cm.sup.3 or less.”, para. [0078]).
Regarding claim 17: In addition to the reasoning used to reject claim 1, Park421 teaches annealing the P-type semiconductor layer to activate magnesium ions of the P-type semiconductor layer. (See Fig. 17B, “the entire impurity containing layer 4000 may be activated by using a thermal annealing process.”, para. [0120]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20150048421 A1), hereinafter referred to as Park421, in view of Khan et al. (US 20100187545 A1) hereinafter referred to as Khan545 and Thomas et al. (US 20240088222 A1) hereinafter referred to as Thomas222.
Regarding claim 3: In addition to the reasoning used to reject claim 1, as best understood, Park421 and Khan545 do not teach that the etching the sacrificial layer comprises: etching the sacrificial layer by in-situ etching.
Thomas222 teaches deposition and etching within the same chamber “The etch process may include any appropriate etch process and be performed in-situ in the same chamber as the subsequent epitaxial deposition process”, para. [0080]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that deposition and etch could be performed in the same process chamber, to arrive at the claimed invention. A person of ordinary skill in the art would recognize the advantage of greater process control and efficiency using this method. Additionally, since a process chamber capable of deposition and etching was well-known in the art, the results would be predictable.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20150048421 A1), hereinafter referred to as Park421, in view of Khan et al. (US 20100187545 A1) hereinafter referred to as Khan545 and Mishra et al. (US 20200119179 A1) hereinafter referred to as Mishra179.
Regarding claim 8: In addition to the reasoning used to reject claim 7, as best understood, Park421 and Khan545 do not teach wherein an etching selectivity ratio of the sacrificial layer to the protection layer is greater than 1, the material of the sacrificial layer comprises any one of: GaN and AIGaN, and the material of the protection layer comprises any one of: AlN and AIGaN.
Mishra179 teaches a sacrificial layer made of GaN (“a GaN mobility enhancement layer 31”, para. [0088]) and a protection layer made of AlGaN (“an AlGaN mobility enhancement layer 32 over the GaN mobility enhancement layer 31.”). In light of the specification, since the sacrificial layer is made of GaN and the protection layer above it made of AlGaN, then the etching selectivity ratio is greater than 1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that doped GaN and AlGaN layers could be used to improve a III-N device (See Mishra179, “The GaN mobility enhancement layer 31 can be unintentionally doped (UID) GaN or the GaN mobility enhancement layer 31 can be doped (e.g., with Si, Fe, C, Mg) to compensate any undesired UID n-type or UID p-type conductivity. The thickness and composition of the GaN layer 31 and AlGaN layer 32 can be selected to optimize mobility and threshold voltage.”, para. [0089]). The high mobility layers taught by Mishra179 could be deposited onto the gate structure taught by Park421 (See Fig 2 annotated above, gate region R10 and G10) to arrive at the claimed device. These layers are also etched “Alternatively, the gate contact 23 can be used as an etch mask to etch the AlGaN layer 32 and the GaN layer 31, such that the regrown III-N layer structure remains directly beneath the gate contact 23 but is etched away, or partially etched away, everywhere else.”, para. [0088]) and can be regrown as desired (See para. [0025]), therefore the doping methods taught by Khan545 could be applied to the device taught by Park421 and Mishra179 to arrive at the claimed invention. Using the methods taught by Khan545 and Mishra179, such a modification could be made with a reasonable expectation of success.
Regarding claim 16: In addition to the reasoning used to reject to claim 1, Park421 and Khan545 do not explicitly teach a P-type layer wherein the P-type semiconductor layer comprises a low-resistance region and the high-resistance region that are stacked along a direction from the substrate to the P-type semiconductor layer, and a concentration of magnesium ions located in the low-resistance region gradually decreases along the direction from the substrate to the P-type semiconductor layer.
Mishra179 teaches the vertical stacking of doped and un-doped regions within a P-type semiconductor layer (“For example, the layer 17 can include a series of p-doped portions in the vertical direction, each separated by undoped portions.”, para. [0062]) and that the dopant may be magnesium (“If the III-N body layer 17 is p-type GaN doped with Mg, the device can be treated with high temperature annealing to render Mg dopants electrically active”, para. [0061]). The undoped regions will necessarily have a higher resistance than the doped regions and, as a result of annealing to activate the mg ions, some ions will necessarily diffuse into the undoped regions producing a gradually decreasing concertation of ions with depth.
Similar to the reasoning used to reject claim 8, the methods of Khan545 and Mishra179 could be used to modify the device taught by Park421 so that the P-type layer region R10 would have a high-resistance region and a low resistance region with the mg ions gradually decreasing along the direction from the substrate to the P-type semiconductor layer to arrive at the claimed invention. Using the teaching of Khan545 and Mishra179, such a modification could be made with a reasonable expectation of success and could be used to establish greater control over the conductive properties of the P-type layer.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20150048421 A1), hereinafter referred to as Park421, in view of Khan et al. (US 20100187545 A1) hereinafter referred to as Khan545 and Sheppard et al. (US 20060019435 A1) hereinafter referred to as Sheppard435.
Regarding claim 9: In addition to the reasoning used to reject claim 7, Park421 and Khan545 do not teach an etching selectivity ratio of the sacrificial layer to the protection layer is less than 1, the material of the sacrificial layer is AlN, and the material of the protection layer is AlGaN.
Sheppard435 teaches a sacrificial layer (encapsulation layer) made of AlN (“The encapsulation layer may include AlN.”, para. [0010]) and a protection layer (cap layer) made of AlGaN (“The cap layer 24 may be a Group III-nitride, and, in some embodiments, a GaN based semiconductor material, such as GaN, AlGAN and/or InGaN.”, para. [0042]). The sacrificial layer is removed after annealing (“the annealing is preceded by forming an encapsulation layer on the third layer of GaN based semiconductor material and in the gate recess. The anneal may be followed by removing the encapsulation layer”, para. [0016]. During the annealing process, dopants will necessarily migrate into the AlN encapsulation layer before it is removed. In light of the specification, if the sacrificial layer is AlN and the protection layer is AlGaN then the etching selectivity ratio is less than 1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an encapsulation layer in the annealing process (See Sheppard435, “The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor.”, abstract), choosing suitable materials for the encapsulation layer, such as AlN, and the protection layer, such as AlGaN. The doping method taught by Khan545 could be modified to include an AlN encapsulation layer and a AlGaN protection layer, using the teaching methods of Sheppard435, with a reasonable chance of success. A person of ordinary skill in the art would recognize that this could prevent damage to the underlying semiconducting layers.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Dunne et al. (US 20080132047 A1) teaches a method for creating a vertically stacked high doping and low doping region. Aktas et al. (US 20190252186 A1) teaches a method of applying a GaN layer, diffusing dopants into the GaN layer, and then removing the GaN layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERT L STEWART/ Examiner, Art Unit 2898
/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
Prosecution Insights