Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-10, drawn to a semiconductor structure, classified in H10W74/134 and H10D30/47.
II. Claims 11-15, drawn to a method for manufacturing a semiconductor structure, classified in H10D30/015.
Inventions Group I and Group II are related as process of making and product made. The
inventions are distinct if either or both of the following can be shown: (1) that the process as
claimed can be used to make another and materially different product or (2) that the product as
claimed can be made by another and materially different process (MPEP § 806.05(f)). In the
instant case the claimed device can be formed by a materially different process than that of the
claimed processes. In particular, the device can be formed without etching, instead using
selective deposition to form the first passivation layer and leave the strip shaped structures.
Restriction for examination purposes as indicated is proper because all the inventions
listed in this action are independent or distinct for the reasons given above and there would be a
serious search and/or examination burden if restriction were not required because one or more of
the following reasons apply:
-The inventions have acquired a separate status in the art in view of their different
classification;
-The inventions have acquired a separate status in the art due to their recognized
divergent subject matter; and/or
-The inventions require a different field of search (e.g., searching different
classes/subclasses or electronic resources, or employing different search strategies or
search queries). In the instant case, the method claims would require searching for
specific etching steps not required by the device claims.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Rejoinder
The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01.
Telephone Communications
During a telephone conversation with Luo, Zhengyun on 5/13/2026 a provisional election was made without traverse to prosecute the invention of Group 1, comprising claims 1-10. Affirmation of this election must be made by applicant in replying to this Office action. Claims 11-15 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Status of Claims
The status of the claims is as follows: Claims 1-15 are pending.
Claims 11-15 are withdrawn. An action on the merits for claims 1-10 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)- (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non- English application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Structure With Strip-Shaped Passivation Layers And Manufacturing Method Thereof.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 20220344485 A1), hereinafter Bao. in view of Kajiwara et al. (US 20200027978 A1), hereinafter Kajiwara and Kaijwara et al. (US 20220231155 A1), hereinafter Kajiwara155.
Regarding Claim 1, Bao teaches a semiconductor structure (“GaN device;” Figs. 8, 9 (partial section of Fig. 8), 10 (partial section of Fig. 8), Paragraph [0066]), comprising:
a substrate (“substrate,” (100); Fig. 8, Paragraph [0066]),
a channel layer (“GaN layer,” (300); Paragraph [0066]),
a barrier layer (“AlGaN layer,” (400); Paragraph [0066]), and
a passivation layer (“passivation layers;” Fig. 9, Paragraph [0068]) that are sequentially stacked; wherein the passivation layer (“passivation layers”) comprises
a first passivation layer (“passivation layers,” (410); Paragraph [0068]) and
the first passivation layer (410) has a plurality of strip-shaped structures (410; Fig. 8, the passivation layer is exclusively made up of strip-shaped structures in this embodiment and the same reference numerals will be used (as the first passivation layer contains strip shaped structures)),
each of the plurality of strip-shaped structures (410; Fig. 8) extends in a first direction (Direction B; Annotated Fig. 8, (see below)), and
a first groove (gap in line with 620) is formed between any two adjacent strip-shaped structures (410) in the plurality of strip-shaped structures (410).
Bao does not explicitly teach a semiconductor structure comprising:
a second passivation layer,
the second passivation layer at least covers the first groove, and
an ability of the second passivation layer to consume a two-dimensional electron gas is greater than an ability of the first passivation layer to consume a two-dimensional electron gas.
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Kajiwara teaches a semiconductor structure (“semiconductor device,” (110); Fig. 1, Paragraph [0023]) comprising at least:
a passivation layer (combined 30, 40),
wherein the passivation layer (combined 30, 40) comprises
a first passivation layer (“nitride layer,” (30); Paragraph [0029]) and
a second passivation layer (“oxide layer,” (40); Paragraph [0029]),
a first groove (separating sections of 30 in Fig. 1) is formed between any two adjacent strip-shaped structures (strip shaped structures of 30) in the plurality of strip-shaped structures (strip shaped structures of 30),
the second passivation layer (40) at least covers the first groove (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bao with the passivation layers of Kajiwara such that the semiconductor device comprises a second passivation layer, the second passivation layer covering the first groove. The addition of a second passivation layer adds the benefit of acting as a gate insulating layer and directly connecting the gate electrode to the barrier layer (Paragraph [0043]). (Note: the proposed modification of Bao involves keeping the structure of Bao where electrodes run perpendicular to the passivation layers in Direction A as opposed to Direction B while adding the multilayer passivation structure of Kajiwara in a rotated manner to be aligned with the arrangement of Bao.)
Bao as modified by Kajiwara additionally does not explicitly teach
Wherein an ability of the second passivation layer to consume a two-dimensional electron gas is greater than an ability of the first passivation layer to consume a two-dimensional electron gas.
Kajiwara155 teaches at least a semiconductor device (“semiconductor device,” (110); Fig. 1, Paragraph [0036]) wherein
an ability of the second passivation layer (“first insulating region,” (42a); Paragraph [0037]) to consume a two-dimensional electron gas is greater than an ability of the first passivation layer (“second insulating region,” (42b); Paragraph [0037]) to consume a two-dimensional electron gas.
(“An ability of a passivation layer to consume a two-dimensional electron gas” is interpreted based on the present specification to be reflected by a higher hydrogen concentration which has an effect of forming a different threshold voltage. This is seen in that Kajiwara155 teaches a passivation layer, or second insulating member, that has the same structural relative hydrogen concentrations (Paragraph [0037]) of the present specification and further teaches the same function as the present specification in stabilizing a threshold voltage in order to improve a high breakdown voltage (Paragraph [0037]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bao as modified by Kajiwara with the teachings of Kajiwara155 such that an ability of the second passivation layer to consume a two-dimensional electron gas is more explicitly greater than an ability of the first passivation layer to consume a two-dimensional electron gas. This is because having the relative hydrogen concentration, which causes the increased consumption of two-dimensional electron gas, of the second passivation layer be higher than that of the first passivation layer suppresses a current collapse of the device, suppresses fluctuations in the threshold voltage, and obtains a high breakdown, or threshold, voltage.
Regarding Claim 2, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1, wherein a hydrogen concentration of the second passivation layer (Kajiwara155, 42a) is greater than a hydrogen concentration of the first passivation layer (Kajiwara155, 42b). (Kajiwara155, “the second insulating region 42b has […] a second hydrogen concentration lower than a first hydrogen concentration in the first insulating region 42a;” Paragraph [0037]. Note: here, Kajiwara155 is being used to further limit the already introduced hydrogen concentrations of the passivation layers.)
Regarding Claim 3, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1, wherein a material of the second passivation layer (Kajiwara, 40) comprises at least one of SiN, SiO2, Al2O3, HfO2, HfZrO, or AlN (Kajiwara, “the oxide layer 40 is, for example, a SiO2 layer;” Paragraph [0039])).
Regarding Claim 4, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 3, wherein a hydrogen concentration of the second passivation layer (40) is greater than or equal to 1E18/cm3 and less than or equal to 1E22/cm3. (“the concentration of hydrogen in the third oxide region 43 is, for example, 2E19/cm3;” Paragraph [0151]; Note: the third oxide region 43 is a component of the oxide layer 40.)
Regarding Claim 6, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1, wherein the first groove (Kajiwara, space separating 30 between third and fourth nitride regions 33 and 34; Fig. 1) and the first passivation layer (Kajiwara, 30) are covered by the second passivation layer (Kajiwara, 40).
Regarding Claim 7, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1, wherein in a plane perpendicular to the first direction (Bao, Direction B), a cross section shape of the first passivation layer comprises at least one of a rectangle (Bao, Fig. 8), a trapezoid, a triangle, or an arc.
Regarding Claim 10, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1, further comprising:
a source electrode (“source,” (S); Fig. 8, Paragraph [0066]) located on the barrier layer (400);
a drain electrode (“drain,” (D) comprising drain metal M; Paragraph [0066]) located on the barrier layer (400), and a direction from the source electrode (S) to the drain electrode (D) being parallel to the first direction (Direction B); and
a gate electrode (“gate,” (G); Paragraph [0066]) located between the source electrode (S) and the drain electrode (D).
Bao does not explicitly teach wherein a gate electrode is located on the passivation layer.
Kajiwara further teaches at least a semiconductor structure (“semiconductor device,” (110); Fig. 1, Paragraph [0023]) comprising:
A gate electrode (“third electrode,” (53) that functions as a gate electrode; Paragraph [0043]) located on the passivation layer (combined 30, 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Bao with the teachings of Kajiwara such that the gate electrode is located on the passivation layer. This allows, contrary to the source and drain electrodes, for the gate electrode to be separated from the barrier layer and for the gate electrode to be insulated by the passivation layer (Paragraph [0043]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Kajiwara and Kajiwara155, and further in view of Cheng (US 20220069113 A1), hereinafter Cheng.
Regarding Claim 5, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1.
Bao as modified by Kajiwara and Kajiwara155 does not explicitly teach wherein a material of the first passivation layer comprises in-situ grown SiN.
Cheng teaches at least a semiconductor structure (“semiconductor structure,” (1); Fig. 1, Paragraph [0046]) wherein a material of the first passivation layer (“in-situ insulating layer,” (12); Paragraph [0047]) comprises in-situ grown SiN (“in-situ insulating layer […] may be one of SiN;” Paragraph [0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bao with the teachings of Cheng such that a material of the first passivation layer comprises in-situ grown SiN. This is because the in-situ first passivation layer can reduce a leakage current and thereby reduce the necessary thickness of the barrier layer. This has the added benefit of reducing the threshold voltage and increasing the working current (Paragraph [0058]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Kajiwara and Kajiwara155, and further in view of Wang et al. (CN 111261714 A), hereinafter Wang. (An attached machine translation of Wang is used for citation purposes)
Regarding Claim 8, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1.
Bao as modified by Kajiwara and Kajiwara155 does not explicitly teach wherein at least two of the plurality of strip-shaped structures have different widths in a direction perpendicular to the first direction and perpendicular to a direction from the substrate to the barrier layer.
Wang teaches at least a semiconductor structure (“gallium nitride power device;” Paragraph [0051]) wherein at least two of the plurality of strip-shaped structures (“passivation layer,” (109); Paragraph [0051]) have different widths (“etch the passivation layer 109 located on the right […] to form a strip-shaped passivation layer with spaced intervals;” Paragraph [0068]; Note: since only the passivation layer 109 on the right is etched into smaller strips, the passivation layer 109 on the left , being unseparated, will have a different width) in a direction perpendicular to the first direction and perpendicular to a direction from the substrate (“silicon substrate,” (101); Fig. 1, Paragraph [0051]) to the barrier layer (“barrier layer,” (108); Paragraph [0051]). (Note: as Wang ultimately modifies the passivation structure of Bao, the passivation layers of Bao have a width in a direction perpendicular to the first direction and perpendicular to a direction from the substrate to the barrier layer; i.e. Bao, Direction A.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bao as modified by Kajiwara with the teachings of Wang such that at least two of the plurality of strip-shaped structures have different widths. Having passivation layers of different widths exposes the underlying barrier layer only in some locations and allows another material to be placed in those gaps in a targeted way. This has the added benefit of controlling where the passivation from the first layer is provided, where it is not, and shields the electric field peak at a certain location. This improves a voltage withstand capacity, making the semiconductor device more reliable (Paragraph [0042]).
Regarding Claim 9, Bao as modified by Kajiwara and Kajiwara155 teaches the semiconductor structure according to claim 1.
Bao as modified by Kajiwara and Kajiwara155 does not explicitly teach wherein in a direction perpendicular to the first direction and perpendicular to a direction from the substrate to the barrier layer, at least two pairs of adjacent strip-shaped in the plurality of strip-shaped structures have different spacing distances.
Wang teaches at least a semiconductor structure (“gallium nitride power device;” Paragraph [0051]) wherein in a direction perpendicular to the first direction and perpendicular to a direction from the substrate (“silicon substrate,” (101); Fig. 1, Paragraph [0051]) to the barrier layer (“barrier layer,” (108); Paragraph [0051]), at least two pairs of adjacent strip-shaped structures (“passivation layer,” (109); Paragraph [0051]) in the plurality of strip-shaped structures (109) have different spacing distances (“spacing between the spaced strips of passivation layers […] decreases sequentially;” Paragraph [0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bao as modified by Kajiwara with the teachings of Wang such that pairs of adjacent strip-shaped structures have different spacing distances. This is because having spaced passivation strips allows gaps for another structure to contact the barrier layer for the added benefit of improving a voltage withstand capacity, making the semiconductor device more reliable (Paragraph [0042]).
Conclusion
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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