Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu et al (US 2018/0294278)
A memory device, comprising:
an array of memory cells (Fig.7 (cube) and [0108]) in an array region (Fig.7 (cube) and [0108]);
word lines (Fig.7 (WLL) and [0109]) extending parallel in a first lateral direction (x-direction);
bit lines (Fig.7 (BL) and [0108]) extending parallel in a second lateral direction (y direction) different from the first lateral direction (x-direction); and
interconnection structures (Fig. 10A-10D) and [0116]) located within the array region and coupled with the bit lines (Fig.7 (BL) and [0108]), and arranged in staggered rows along the first lateral direction [0116-0117].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al (US 2023/0371244).
A memory device, comprising:
an array of memory cells (Fig.2A (200/204) and [0083-0085]) in an array region [0130] ;
word lines (Fig.12B (1238) and [0150]) extending parallel in a first lateral direction (x-direction);
bit lines (Fig.11I/12C (1128/1228) and [0144/0154]) extending parallel in a second lateral direction (y direction) different from the first lateral direction (x-direction); and
interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) located within the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.
2. The memory device of claim 1, wherein: a first distance between two interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) coupled with two adjacent bit lines (Fig.11I/12C (1128/1228) and [0144/0154]) is greater than a second distance between the two adjacent bit lines (Fig.11I/12C (1128/1228) and [0144/0154]).
3. The memory device of claim 1, wherein: a first row of interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) are located at a first side of a center position of the array region; and a second row of interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) are located at a second side of the center position opposite to the first side (Fig. 11J/12D (1132/1232) and [0146-0148]).
4. The memory device of claim 1, wherein: a first row of interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) are located at a first side of one word line (Fig.12B (1238) and [0150]); and a second row of interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) are located at a second side of the one word line (Fig.12B (1238) and [0150]) opposite to the first side.
5. The memory device of claim 1, wherein: each of the array of memory cells comprises a vertical transistor (Fig. 11J/12C (1114/1204) and [0151]) and a storage unit (Fig. 11J/12C (1116/1216/1234) and [0154] coupled with the vertical transistor (Fig. 11J/12C (1114/1204) and [0151]); and
gate structures (Fig.4 (416) and [0101-0103]) of each row of vertical transistors (Fig. 11J/12C (1114/1204) and [0151]/ (Fig. 4 (410) and [0101])) aligned along the first lateral direction are connected with each other to constitute a corresponding word line (Fig.12B (1238) and [0150]).
6. The memory device of claim 5, wherein the gate structures (Fig.4 (416) and [0101-0103]) of each row of vertical transistors (Fig. 4 (410) and [0101]) are located on a lateral side of channel structures [0101] of the row of vertical transistors (Fig. 4 (410) and [0101]).
7. The memory device of claim 6, wherein each gate structure (Fig.4 (416) and [0103]) laterally surrounds a corresponding channel structure (Fig. 4 (414) and [0103]).
8. The memory device of claim 7, further comprising: a conductive layer (Fig. 11J/12D (1128/1228) and [0146-0148]) connected to first ends of the interconnection structures (Fig. 11J/12D (1132/1232) and [0146-0148]), wherein second ends of the interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) are connected to the bit lines (Fig.11I/12C (1128/1228) and [0144/0154]); and an insulating layer (Fig.11J (1130) and [0146]) between the bit lines (Fig.11I/12C (1128/1228) and [0144/0154]) and the conductive layer, wherein the interconnection structures (Fig. 11J/12D (1132/1128/1228/1232) and [0146-0148]) vertically extend through the insulating layer (Fig.11J (1130) and [0146]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhu et al (US 20240332232); Liu et al (US 20230062524) and Yang et al (US 20230134556) teach similar memory cell structures with vertical transistors.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
7/24/26
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