DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the second semiconductor chip being spaced apart, in a first direction, from the first substrate, the first direction being parallel to a top surface of the first substrate” (claim 1; emphasis added) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites “the second semiconductor chip being spaced apart, in a first direction, from the first substrate, the first direction being parallel to a top surface of the first substrate” (emphasis added). It is unclear how a chip could be both on the substrate and, specifically in the direction claimed, spaced apart from it. It is the examiner’s opinion, in light of the specification, drawings, and analogous language of other claims, that this limitation contains a typo and should be corrected to recite “the second semiconductor chip being spaced apart, in a first direction, from the first semiconductor chip in a vertical direction
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suk et al. (US 20220102282 A1, hereinafter S1), and further in view of Suthram et al. (US 20240222328 A1, hereinafter S2).
Regarding independent claim 1, S1 discloses in S1 FIG. 1, 2C and 9 A semiconductor package comprising: a first substrate (substrate 100); a first chip on the first substrate (capacitor chip 400); a second chip on the first substrate (another capacitor chip 400; although only one element is labeled 400 in S1’s cross-sectional figures, it is clear from S1 FIG. 1 that the identical unlabeled structure corresponds to capacitor chip 400) the second semiconductor chip being spaced apart from the first substrate in a vertical direction (second chip 400 is vertically spaced apart from substrate 100); at least one thermal radiation structure on the first substrate and between the first chip and the second chip (stack via SP is considered a thermal radiation structure because it is capable of functioning as a thermal radiation structure according to the understood meaning of said term in the art as a thermally conductive structure. Stack via SP is inherently thermally conductive due to its material composition including high thermal conductivity metals such as copper or aluminum (S1 [0033], [0036]) and is therefore inherently a thermal radiation structure.); and a third semiconductor chip on the first chip, the second chip, and the at least one conductive via (first semiconductor chip 210 is in the position described), wherein the at least one thermal radiation structure comprises: a thermal radiation post (lower portion of stack via SP as shown in the annotated figure below); and a thermal conductive pattern on the thermal radiation post (upper portion of stack via SP as shown in the annotated figure below), wherein a bottom surface of the third semiconductor chip is in contact with the thermal conductive pattern (the upper portion of stack via SP contacts the bottom surface of semiconductor chip 210 including first and second chip pads 213/215 and first connection terminals 350), and wherein a top surface of the first substrate is in contact with the thermal radiation post (stack via SP contacts substrate 100 on its dielectric layer 103, which is considered a top surface of the substrate because there are no overlying layers of substrate 100 in the region on which chips 400 and stack via SP are formed).
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S1 does not explicitly disclose the first and second chips are semiconductor chips.
However, in the same field of endeavor, S2 discloses in S2 Fig. 7A and associated text semiconductor chips (IC dies 704 and 706 are considered semiconductor chips at least because they are ICs, which include semiconductor material (S2 [0002])). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of S1 with the substitution of S1’s capacitor chips 400 with S2’s semiconductor chips to provide a three-dimensional integrated circuit package with additional semiconductor chips designed to perform specialized functions, which improves the versatility of the package.
Regarding dependent claim 5, S1, as modified by S2, further discloses The semiconductor package of claim 1, wherein a portion of the bottom surface of the third semiconductor chip is in contact with a portion of a top surface of the first semiconductor chip and a portion of a top surface of the second semiconductor chip (the bottom surface of semiconductor chip 210, including first and second chip pads 213/215 and first connection terminals 350, contacts the top surfaces 400a of both chips 400).
Regarding dependent claim 6, S1, as modified by S2, further discloses in S1 FIG. 2C The semiconductor package of claim 1, wherein the first substrate comprises an upper pad on an upper portion of the first substrate (the barrier pattern 171 at the bottom of stack via SP is a pad on dielectric layer 103, which is an upper portion of the substrate 100, as interpreted above), wherein a top surface of the upper pad protrudes from the top surface of the first substrate (the aforementioned barrier pattern 171 protrudes as shown in S1 FIG. 2C), and wherein a bottom surface of the thermal radiation post is in contact with the top surface of the upper pad (a bottom surface of conductive pattern 173 at the bottom of stack via SP is in contact with the aforementioned barrier pattern 171).
Regarding dependent claim 7, S1, as modified by S2, further discloses the semiconductor package of claim 1, wherein the third semiconductor chip is a logic chip (the first semiconductor chip 210 may be one of a logic chip… (S1 [0051])).
Regarding dependent claim 12, S1, as modified by S2, further discloses the semiconductor package of claim 1, wherein the thermal radiation post comprises copper (stack via SP, including the portion corresponding to the thermal radiation post, as interpreted above, may be substantially the same as upper conductive patterns 150 which may be copper (S1 [0033], [0036])).
Regarding dependent claim 13, S1, as modified by S2, further discloses The semiconductor package of claim 1, wherein the thermal conductive pattern comprises at least one of aluminum (Al), aluminum oxide (Al2O3), aluminum nitride (AlN), magnesium oxide (MgO), silicon carbide (SiC), and silicon (Si) (stack via SP, including the portion corresponding to the thermal conductive pattern, as interpreted above, may be substantially the same as upper conductive patterns 150 which may be aluminum (S1 [0033], [0036])).
Regarding independent claim 14, S1 discloses A semiconductor package comprising: a first substrate (substrate 100); a first chip on the first substrate (capacitor chip 400); a second chip on the first substrate, the second chip being spaced apart in a first direction from the first chip, the first direction being parallel to a top surface of the first substrate (another capacitor chip 400 spaced apart from the first in direction D1; although only one element is labeled 400 in S1’s cross-sectional figures, it is clear from S1 FIG. 1 that the identical unlabeled structure corresponds to capacitor chip 400); at least one thermal radiation structure on the first substrate and between the first chip and the second chip (stack via SP is considered a thermal radiation structure because it is capable of functioning as a thermal radiation structure according to the understood meaning of said term in the art as a thermally conductive structure. Stack via SP is inherently thermally conductive due to its material composition including high thermal conductivity metals such as copper or aluminum (S1 [0033], [0036]) and is therefore inherently a thermal radiation structure.); and a third semiconductor chip on the first chip, the second chip, and the at least one thermal radiation structure (first semiconductor chip 210 is in the position described), wherein the at least one thermal radiation structure comprises: a thermal radiation post (lower portion of stack via SP as shown in the annotated figure below); and a thermal conductive pattern on the thermal radiation post (upper portion of stack via SP as shown in the annotated figure below), wherein the third semiconductor chip comprises: a wiring layer (first and second chip pads 213/215 and first connection terminal 350 are interpreted as a wiring layer); and a circuit layer on the wiring layer (semiconductor chip 210 includes integrated circuits (not shown) adjacent to bottom surface 210b, which is on the wiring layer as interpreted above. At least the portion of semiconductor chip 210 adjacent to its bottom surface 210b is therefore interpreted as a circuit layer and any other portions of semiconductor chip 210 containing circuits would similarly be considered a part of the circuit layer), wherein the thermal conductive pattern is in contact with the wiring layer (the portion of stack via SP corresponding to the thermal conductive pattern is in contact with first connection terminal 350 and therefore the wiring layer as interpreted above). S1 does not explicitly disclose the first and second chips are semiconductor chips or the circuit layer comprises a plurality of circuit regions, wherein the at least one thermal radiation structure overlaps, in a second direction, with at least one of the plurality of circuit regions, the second direction being perpendicular to the top surface of the first substrate.
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However, in the same field of endeavor, S2 discloses in S2 Fig. 7A and associated text semiconductor chips (IC dies 704 and 706 are considered semiconductor chips at least because they are ICs, which include semiconductor material (S2 [0002])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of S1 with the substitution of S1’s capacitor chips 400 with S2’s semiconductor chips to provide a three-dimensional integrated circuit package with additional semiconductor chips designed to perform specialized functions, which improves the versatility of the package.
Additionally, S2 discloses in S2 FIG. 2 and associated text the circuit layer comprises a plurality of circuit regions (a layer of IC die 100 comprises active regions 108 and 114, which each comprise transistors (S2 [0090]), therefore interpreted as circuit regions, which notably extend over the full width of IC die 100).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the semiconductor package including semiconductor chips of S1, as previously modified by S2, with the circuit regions of S2 to provide the third semiconductor chip with a plurality of circuit regions, which allows mixed use of manufacturing processes for different nodes or kinds of circuits in the chip (S2 [0091]). As combined, this would result in the at least one thermal radiation structure overlaps, in a second direction, with at least one of the plurality of circuit regions, the second direction being perpendicular to the top surface of the first substrate because the circuit regions of S1’s semiconductor chip 210 would extend across its full width as taught by S2 and noted above, meaning any position of S1’s stack via SP under chip 210 would overlap at least one of the circuit regions as claimed.
Regarding dependent claim 15, S1, as modified by S2, discloses in S1 FIG. 9 and associated text The semiconductor package of claim 14, further comprising a fourth semiconductor chip on the third semiconductor chip (semiconductor chip 220, corresponding to a fourth semiconductor chip is on semiconductor chip 210, the third semiconductor chip), wherein the third semiconductor chip is a logic chip (integrated circuits in semiconductor chip 210 may include a logic circuit (S1 [0041]), making semiconductor chip 210 a logic chip). S1, as previously modified by S2, does not explicitly disclose the fourth semiconductor chip is a static random access memory (SRAM).
However, in the same field of endeavor, S2 discloses in S2 FIG. 9 and associated text the fourth semiconductor chip is a static random access memory (SRAM) (IC die 100 comprises SRAM circuits (S2 [0099])).
Before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to use an SRAM-configured chip as the fourth semiconductor chip because Applicant has not disclosed that the fourth semiconductor chip being SRAM provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with another kind of memory chip because other memory chips are known in the art for performing the same general function. Therefore, it would have been an obvious matter of design choice to use any kind of memory chip best suited for the design specifications including S2’s SRAM chip.
Regarding dependent claim 16, S1, as modified by S2, discloses the semiconductor package of claim 14. S1, as modified by S2, does not explicitly disclose at least one of the first semiconductor chip and the second semiconductor chip is a mobile chip or an analog chip.
However, in the same field of endeavor, S2 discloses in S2 FIG. 17 and associated text at least one semiconductor chip is a mobile chip or an analog chip (communication chip 2412 may be one of a variety of kinds of analog chips such as Wi-Fi (S2 [0138])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of S1, as previously modified by S2, with the analog communication chip of S2 as one of the first or second semiconductor chips to provide a semiconductor package with additional functionality such as wireless communication over a variety of protocols (S2 [0137]).
Regarding dependent claim 17, S1, as modified by S2, further discloses in S1 FIG. 9 and associated text The semiconductor package of claim 14, further comprising a second substrate above the first substrate (intermediate dielectric layer 370), wherein the second substrate is above the third semiconductor chip (intermediate dielectric layer 370 is above semiconductor chip 210), and wherein the at least one thermal radiation structure is spaced apart, in the second direction, from the second substrate (stacked via SP is spaced apart from intermediate dielectric layer 370 in D3).
Regarding dependent claim 18, S1, as modified by S2, further discloses in S1 FIG. 9 and associated text The semiconductor package of claim 17, further comprising: a package substrate on the second substrate (redistribution substrate 500 is a substrate of package 2); and a fifth semiconductor chip on the package substrate (semiconductor chip 220 is on redistribution substrate 500), wherein the fifth semiconductor chip is a memory chip (semiconductor chip 220 may be a high bandwidth memory chip (S1 [0051])).
Regarding independent claim 19, S1 discloses A semiconductor package comprising: a first redistribution substrate (first redistribution substrate 100); a second redistribution substrate on the first redistribution substrate (second redistribution substrate 500); a first chip on the first redistribution substrate (capacitor chip 400); a second chip on the first redistribution substrate, the second chip being spaced apart, in a first direction, from the first chip, the first direction being parallel to a top surface of the first redistribution substrate (another capacitor chip 400 spaced apart from the first in direction D1; although only one element is labeled 400 in S1’s cross-sectional figures, it is clear from S1 FIG. 1 that the identical unlabeled structure corresponds to capacitor chip 400); a third semiconductor chip on the first chip and the second chip (first semiconductor chip 210 is in the position described), a portion of a bottom surface of the third semiconductor chip being in contact with a portion of a top surface of the first chip and a portion of a top surface of the second chip (the bottom surface of semiconductor chip 210, including first and second chip pads 213/215 and first connection terminals 350, contacts the top surfaces 400a of both chips 400); and at least one thermal radiation structure below the third semiconductor chip, the at least one thermal radiation structure being between the first semiconductor chip and the second semiconductor chip (stack via SP, which is in the position described, is considered a thermal radiation structure because it is capable of functioning as a thermal radiation structure according to the understood meaning of said term in the art as a thermally conductive structure. Stack via SP is inherently thermally conductive due to its material composition including high thermal conductivity metals such as copper or aluminum (S1 [0033], [0036]) and is therefore inherently a thermal radiation structure.), wherein the third semiconductor chip comprises: a wiring layer (first and second chip pads 213/215 and first connection terminal 350 are interpreted as a wiring layer); and a circuit layer on the wiring layer (semiconductor chip 210 includes integrated circuits (not shown) adjacent to bottom surface 210b, which is on the wiring layer as interpreted above. At least the portion of semiconductor chip 210 adjacent to its bottom surface 210b is therefore interpreted as a circuit layer and any other portions of semiconductor chip 210 containing circuits would similarly be considered a part of the circuit layer), wherein the at least one thermal radiation structure comprises: a thermal radiation post (lower portion of stack via SP as shown in the annotated figure below); and a thermal conductive pattern on the thermal radiation post (upper portion of stack via SP as shown in the annotated figure below), wherein the thermal conductive pattern is in contact with the wiring layer (the portion of stack via SP corresponding to the thermal conductive pattern is in contact with first connection terminal 350 and therefore the wiring layer as interpreted above). S1 does not explicitly disclose the first and second chips are semiconductor chips or the circuit layer comprises a plurality of circuit regions, wherein the at least one thermal radiation structure overlaps, in a second direction, with at least one of the plurality of circuit regions, the second direction being perpendicular to the top surface of the first substrate.
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However, in the same field of endeavor, S2 discloses in S2 Fig. 7A and associated text semiconductor chips (IC dies 704 and 706 are considered semiconductor chips at least because they are ICs, which include semiconductor material (S2 [0002])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of S1 with the substitution of S1’s capacitor chips 400 with S2’s semiconductor chips to provide a three-dimensional integrated circuit package with additional semiconductor chips designed to perform specialized functions, which improves the versatility of the package.
Additionally, S2 discloses in S2 FIG. 2 and associated text the circuit layer comprises a plurality of circuit regions (a layer of IC die 100 comprises active regions 108 and 114, which each comprise transistors (S2 [0090]), therefore interpreted as circuit regions, which notably extend over the full width of IC die 100).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the semiconductor package including semiconductor chips of S1, as previously modified by S2, with the circuit regions of S2 to provide the third semiconductor chip with a plurality of circuit regions, which allows mixed use of manufacturing processes for different nodes or kinds of circuits in the chip (S2 [0091]). As combined, this would result in the at least one thermal radiation structure overlaps, in a second direction, with at least one of the plurality of circuit regions, the second direction being perpendicular to the top surface of the first substrate because the circuit regions of S1’s semiconductor chip 210 would extend across its full width as taught by S2 and noted above, meaning any position of S1’s stack via SP under chip 210 would overlap at least one of the circuit regions as claimed.
Regarding dependent claim 20, S1, as modified by S2, further discloses in S1 FIG. 7 and 9 and associated text The semiconductor package of claim 19, further comprising: a molding layer on the first redistribution substrate (molding layer 360 and under-fill layer 300, which is considered a molding layer because it comprises the same materials as adjacent molding layer 360 and molding layer 290, which is in S1 FIG. 7, and because it performs a substantially similar function to molding layer 290: encapsulating connection terminals 350 and capacitor chips 400 (S1 [0055]-[0057], and [0072])); and a conductive pillar that penetrates the molding layer and electrically connects the first redistribution substrate with the second redistribution substrate (The conductive structure 365 may penetrate the first upper molding layer 360….conductive structure 365 may electrically connect the first redistribution substrate 100 to the second redistribution substrate 500 (S1 [0081])), wherein the molding layer fills a first area between the at least one thermal radiation structure and the first semiconductor chip and a second area between the at least one thermal radiation structure and the second semiconductor chip (under-fill layer 300 fills the areas described), and wherein a first height in the second direction of the at least one thermal radiation structure is less than a second height in the second direction of the conductive pillar (the heights of conductive structure 365 and stack via SP have the relationship described as shown).
Claims 2-3, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over S1, and further in view of S2 and Enomoto et al. (US 20010049187 A1, hereinafter E1).
Regarding dependent claim 2, S1, as modified by S2, discloses the semiconductor package of claim 1, wherein the at least one thermal radiation structure has a first width in the first direction (stack via SP has a width in D1). The combined references do not explicitly disclose the first width is in a range of about 150 μm to about 250 μm.
However, in the same field of endeavor, E1 discloses in E1 FIG. 13 and associated text a via wherein the first width is in a range of about 150 μm to about 250 μm (The diameter of the via 43 is formed to be 20 μm to 250 μm (E1 [0127])). Additionally, it is well-known that the dimensions of a structure are variables which affect the thermal conduction through said structure.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to try a variety of dimensions of S1’s stack via SP, including those in the claimed range, with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding dependent claim 3, S1, as modified by S2, discloses in S1 The semiconductor package of claim 1, wherein the at least one thermal radiation structure has a first height in a second direction perpendicular to the top surface of the first substrate (stack via SP has a height in D3). The combined references do not explicitly disclose the first height is in a range of about 160 μm to about 230 μm.
However, in the same field of endeavor, E1 discloses in E1 FIG. 13 and associated text a via wherein the first height is in a range of about 160 μm to about 230 μm (the height of via 43 is in the range of 15 μm to 200 μm (E1 [0127])). Additionally, it is well-known that the dimensions of a structure are variables which affect the thermal conduction through said structure.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to try a variety of dimensions of S1’s stack via SP, including those disclosed by E1, which overlaps the claimed range, with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding dependent claim 8, S1, as modified by S2 and E1, further discloses The semiconductor package of claim 3, further comprising a second substrate above the first substrate (second redistribution substrate 500), wherein the second substrate is above the third semiconductor chip (substrate 500 is above semiconductor chip 210), and wherein the at least one thermal radiation structure is spaced apart, in the second direction, from the second substrate (stacked via SP is spaced apart from substrate 500 in D3).
Regarding dependent claim 9, S1, as modified by S2 and E1, further discloses in S1 FIG. 7 and 9 and associated text The semiconductor package of claim 8, further comprising: a molding layer on the first substrate (molding layer 360 and under-fill layer 300, which is considered a molding layer because it comprises the same materials as adjacent molding layer 360 and molding layer 290, which is in S1 FIG. 7, and because it performs a substantially similar function to molding layer 290: encapsulating connection terminals 350 and capacitor chips 400 (S1 [0055]-[0057], and [0072])); and a conductive pillar that penetrates the molding layer and electrically connects the first substrate with the second substrate (The conductive structure 365 may penetrate the first upper molding layer 360….conductive structure 365 may electrically connect the first redistribution substrate 100 to the second redistribution substrate 500 (S1 [0081])).
Regarding dependent claim 10, S1, as modified by S2 and E1, further discloses in S1 FIG. 9 and associated text The semiconductor package of claim 9, wherein the molding layer fills a first area between the at least one thermal radiation structure and the first semiconductor chip and a second area between the at least one thermal radiation structure and the second semiconductor chip (under-fill layer 300 fills the areas described), and wherein the first height in the second direction of the at least one thermal radiation structure is less than a second height in the second direction of the conductive pillar (the heights of conductive structure 365 and stack via SP have the relationship described as shown).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over S1, and further in view of S2, E1, and Lee et al. (US 20170287856 A1, hereinafter L1).
Regarding dependent claim 4, S1, as modified by S2 and E1, discloses the semiconductor package of claim 3, wherein the thermal radiation post has a second height in the second direction, and wherein the thermal conductive pattern has a third height in the second direction (portions of stack via SP corresponding to the thermal radiation post and conductive pattern as interpreted above each have heights in D3). The combined references do not explicitly disclose the second height is in a range of about 100 μm to about 150 μm, or the third height is in a range of about 60 μm to about 80 μm.
However, in the same field of endeavor, L1 discloses in L1 FIG. 5 and associated text the second height is in a range of about 100 μm to about 150 μm (the height of through-wiring 115, corresponding to the thermal radiation post, corresponds to the height of frame 110 which is in the range of 100 μm to 500 μm (L1 [0046])), and the third height is in a range of about 60 μm to about 80 μm (the height of wiring layer 113, corresponding to the thermal conductive pattern, is not particularly limited, but may be, for example, about 10 μm to 50 μm (L1 [0048]), which is considered to be “about” 60 μm to about 80 μm). Additionally, it is well-known that the dimensions of a structure are variables which affect the thermal conduction through said structure.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to try a variety of dimensions of S1’s stack via SP, including those disclosed by L1, which overlap the claimed ranges, with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over S1, and further in view of S2 and Liu et al. (US 20240047436 A1, hereinafter L2).
Regarding dependent claim 11, S1, as modified by S2, discloses the semiconductor package of claim 1. The combined references do not explicitly disclose the at least one thermal radiation structure corresponds to two thermal radiation structures, or the two thermal radiation structures are spaced apart from each other, in the first direction, between the first semiconductor chip and the second semiconductor chip.
However, in the same field of endeavor, L2 discloses in L2 FIG. 1G and 6A and associated text the at least one thermal radiation structure corresponds to two thermal radiation structures (thermal-dissipating structures 196 are used as an alternative to a single thermal-dissipating feature 296, which is in L2 FIG. 1G, corresponding to S1’s single stack via SP), and the two thermal radiation structures are spaced apart from each other, in the first direction (thermal-dissipating structures 196 are spaced apart from each other in L2 FIG. 1G as shown).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of S1, as modified by S2, with the two (or more) thermal-dissipating structures of L2 in place of S1’s single stack via SP, which would result in the two thermal radiation structures being between the first semiconductor chip and the second semiconductor chip to provide a semiconductor package with the advantage that additional thermally conductive paths could transfer more heat at once than a single thermal radiation structure or distribute heat to different areas of the substrate. Additionally, it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 11127650 B2, pertaining to heat-dissipation structures between semiconductor chips; and
US 20210343681 A1, pertaining to a stacked semiconductor chip structure similar to that claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights