DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 9, 12, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li, CN 106410773.
Regarding claim 1, Li discloses a power clamp circuit comprising:
an electro-static discharge (ESD) current discharge circuit [Fig. 2, 1] including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage [Fig. 2, three transistors of 14 are connected in series between the voltage rail and VSS];
a first triggering circuit [Fig. 2, first set of RC circuit of 12] including a first resistor [Fig. 2, first R as shown], a first capacitor [Fig. 2, first capacitor as shown] and a fourth MOS transistor [Fig. 2, a transistor of first inverter set of 13] and configured to trigger the first MOS transistor [Fig. 2, triggers the top/first transistor of 14];
a second triggering circuit [Fig. 2, second set of RC circuit of 12] including a second resistor [Fig. 2, second resistor as shown], a second capacitor [Fig. 2, second capacitor as shown], and a fifth MOS transistor [Fig. 2, a transistor of second inverter set of 13] and configured to trigger the second MOS transistor [Fig. 2, triggers the middle/second transistor of 14]; and
a third triggering circuit [Fig. 2, third set of RC circuit of 12] including a third resistor and a third capacitor [Fig. 2, third resistor and capacitor as shown], and configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs [the third/bottom transistor is turned off during normal operation, and turned on during an ESD event to discharge the ESD current].
Regarding claim 2, Li discloses that the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively [Fig. 2 and Fig. 3; discharging transistors of 14 are NMOS as shown],
wherein a gate of the first NMOS transistor is coupled to a first gate line [Fig. 2, line connected between the output of the first inverter set and gate of the first discharge transistor], a drain of the first NMOS transistor is coupled to the first power rail [Fig. 2 and Fig. 3, drain of MN7 is coupled to VDD] and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor [Fig. 3, source of MN7 is coupled to the drain of the middle/second discharge transistor];
wherein a gate of the second NMOS transistor is coupled to a second gate line [Fig. 3, line connected between the output of the second inverter set and the gate of second discharge transistor], and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor [Fig. 3, source of second/middle transistor is coupled to the drain of the bottom/third NMOS transistor], and
wherein a gate of the third NMOS transistor is coupled to a third gate line [Fig. 3, line connected between the output of the third inverter set and the gate of the bottom/third transistor] and a source of the third NMOS transistor is coupled to the second power rail [Fig. 3, source of the third transistor is coupled to VSS].
Regarding claim 3, Li discloses that the first triggering circuit is configured to: provide a first branch voltage generated by branching the supply voltage to the first gate line, and provide an ESD voltage to the first gate line when the ESD event occurs [Fig. 3, R1C1 provides a first branch voltage at node f by branching the supply voltage 3VDD to the first inverter set and then provide the inverted voltage to the first gate line (gate of the first transistor MN7], and wherein the second triggering circuit is configured to: provide a second branch voltage generated by branching the supply voltage to the second gate line, and provide an ESD voltage to the second gate line when the ESD event occurs [Fig. 3, second set of RC circuit is configured to provide a second branch voltage at node g, by branching the supply voltage VB0 (which is 2VDD) to the second inverter set and the provides the inverted voltage to the second gate line (gate of the second discharge transistor].
Regarding claim 4, Li further comprises a voltage branch circuit [Fig. 3, diode-connected transistors 21] configured to provide the first branch voltage [Fig. 3, VB0] and the second branch voltage [VB1], wherein the voltage branch circuit includes a plurality of diode-connected MOS transistors coupled in series between the first power rail and the second power rail.
Regarding claim 6, Li discloses that the first resistor is disposed between the first power rail and a first node [Fig. 3, R1 is disposed between VDD and node f], the first capacitor is disposed between the first node and the second power rail [Fig. 3, C1 is disposed between the node f and VSS], and the fourth MOS transistor [Fig. 3, MP1] is a first P-channel type (PMOS) transistor, and wherein a gate of the first PMOS transistor is coupled to the first node [Fig. 3, gate of MP1 is coupled to the node f], a source of the first PMOS transistor is coupled to the first power rail [Fig. 3, source of MP1 is coupled to VDD], and a drain of the first PMOS transistor is coupled to the first gate line [Fig. 3, drain of MP1 is electrically coupled to the first gate line at node A].
Regarding claim 9, Li discloses that the second resistor is disposed between the first gate line and a second node [Fig. 3, R2 is coupled between the node A and node g], the second capacitor is disposed between the second node and the second power rail [Fig. 3, C2 is disposed between the node g and VSS], and the fifth MOS transistor is a second PMOS transistor, [Fig. 3, top PMOS transistor of a second inverter set connected to the output at node g] and wherein a gate of the second PMOS transistor is coupled to the second node, a source of the second PMOS transistor is coupled to the first gate line, and a drain of the second PMOS transistor is coupled to the second gate line [Fig. 3, gate of PMOS transistor is coupled to the node g, the source of the second PMOS transistor is coupled to the first gate line at node A, and drain terminal of the second PMOS transistor is coupled to the second gate line at node B].
Regarding claim 12, Li discloses that the third triggering circuit is configured to: provide the ground voltage to the third gate line, and provide an ESD voltage to the third gate line when the ESD event occurs [Fig. 3, third NMOS discharge transistor is turned off during normal operation and the third set of RC circuit triggers the gate of the third discharge transistor during an ESD condition].
Regarding claim 15, Li discloses an electronic device comprising:
a pad [Fig. 3 and Fig. 5, input/output pad of the circuit];
an internal circuit coupled to the pad [IC is inherently coupled to the pad and ESD circuit], a first power rail through which a supply voltage is provided [Fig. 3. VDD], and a second power rail [Fig. 3, VSS] through which a ground voltage is provided; and
a power clamp circuit configured to protect the internal circuit when an electro-static discharge (ESD) event occurs, wherein the power clamp circuit includes:
an electro-static discharge (ESD) current discharge circuit [Fig. 2, 1] including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage [Fig. 2, three transistors of 14 are connected in series between the voltage rail and VSS];
a first triggering circuit [Fig. 2, first set of RC circuit of 12] including a first resistor [Fig. 2, first R as shown], a first capacitor [Fig. 2, first capacitor as shown] and a fourth MOS transistor [Fig. 2, a transistor of first inverter set of 13] and configured to trigger the first MOS transistor [Fig. 2, triggers the top/first transistor of 14];
a second triggering circuit [Fig. 2, second set of RC circuit of 12] including a second resistor [Fig. 2, second resistor as shown], a second capacitor [Fig. 2, second capacitor as shown], and a fifth MOS transistor [Fig. 2, a transistor of second inverter set of 13] and configured to trigger the second MOS transistor [Fig. 2, triggers the middle/second transistor of 14]; and
a third triggering circuit [Fig. 2, third set of RC circuit of 12] including a third resistor and a third capacitor [Fig. 2, third resistor and capacitor as shown], and configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs [the third/bottom transistor is turned off during normal operation, and turned on during an ESD event to discharge the ESD current].
Regarding claim 16, Li discloses that the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively [Fig. 2 and Fig. 3; discharging transistors of 14 are NMOS as shown],
wherein a gate of the first NMOS transistor is coupled to a first gate line [Fig. 2, line connected between the output of the first inverter set and gate of the first discharge transistor], a drain of the first NMOS transistor is coupled to the first power rail [Fig. 2 and Fig. 3, drain of MN7 is coupled to VDD] and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor [Fig. 3, source of MN7 is coupled to the drain of the middle/second discharge transistor];
Regarding claim 17, Li discloses that the first triggering circuit is configured to: provide a first branch voltage generated by branching the supply voltage to the first gate line, and provide an ESD voltage to the first gate line when the ESD event occurs [Fig. 3, R1C1 provides a first branch voltage at node f by branching the supply voltage 3VDD to the first inverter set and then provide the inverted voltage to the first gate line (gate of the first transistor MN7], and wherein the second triggering circuit is configured to: provide a second branch voltage generated by branching the supply voltage to the second gate line, and provide an ESD voltage to the second gate line when the ESD event occurs [Fig. 3, second set of RC circuit is configured to provide a second branch voltage at node g, by branching the supply voltage VB0 (which is 2VDD) to the second inverter set and the provides the inverted voltage to the second gate line (gate of the second discharge transistor].
Allowable Subject Matter
Claims 5, 7-8, 10-11, 13-14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 5: The prior art does not disclose that the voltage branch circuit is configured to: provide the first branch voltage of at least 60% of a voltage applied to the first power rail, and provide the second branch voltage of at least 30% of a voltage applied to the first power rail. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement for reasons for allowance of claim 7: The prior art does not disclose that the first triggering circuit further includes a sixth MOS transistor and a seventh MOS transistor that are disposed between the first power rail and the first gate line, and the sixth MOS transistor and the seventh MOS transistor are a fourth NMOS transistor and a fifth NMOS transistor, respectively, wherein a gate of the fourth NMOS transistor is coupled to the first branch voltage, a drain of the fourth NMOS transistor is coupled to the first power rail, and a source of the fourth NMOS transistor is coupled to a gate of the fifth NMOS transistor, and wherein a drain of the fifth NMOS transistor is coupled to the first branch voltage, and a source of the fifth NMOS transistor is coupled to the first gate line. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 8: The prior art does not disclose that the first triggering circuit further includes an eighth MOS transistor and a ninth MOS transistor that are disposed between the first node and the first capacitor, and the eighth MOS transistor and the ninth MOS transistor are a sixth NMOS transistor and a seventh NMOS transistor, respectively, wherein a gate of the sixth NMOS transistor is coupled to the first gate line, a drain of the sixth NMOS transistor is coupled to the first node, and a source of the sixth NMOS transistor is coupled to a drain of the seventh NMOS transistor, and wherein a gate of the seventh NMOS transistor is coupled to the second gate line, and a source of the seventh NMOS transistor is coupled to the first capacitor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 10: The prior art does not disclose that the second triggering circuit further includes a tenth MOS transistor and an eleventh MOS transistor that are disposed between the first gate line and the second gate line, and the tenth MOS transistor and the eleventh MOS transistor are an eighth NMOS transistor and a ninth NMOS transistor, respectively, wherein a gate of the eighth NMOS transistor is coupled to the second branch voltage, a drain of the eighth NMOS transistor is coupled to the first gate line, and a source of the eighth NMOS transistor is coupled to a gate of the ninth NMOS transistor, and wherein a drain of the ninth NMOS transistor is coupled to the second branch voltage, and a source of the ninth NMOS transistor is coupled to the second gate line. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 11: The prior art does not disclose that the second triggering circuit further includes a twelfth MOS transistor disposed between the second node and the second capacitor, and the twelfth MOS transistor is a tenth NMOS transistor, and wherein a gate of the tenth NMOS transistor is coupled to the second gate line, a drain of the tenth NMOS transistor is coupled to the second node, and a source of the tenth NMOS transistor is coupled to the second capacitor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 13: The prior art does not disclose that the third resistor is disposed between the third gate line and a third node. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 14: The prior art does not disclose that a product of a resistance of the first resistor and a capacitance of the first capacitor is equal to a product of a resistance of the second resistor and a capacitance of the second capacitor and a product of a resistance of the third resistor and a capacitance of the third capacitor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 18: The prior art does not disclose that the first triggering circuit further includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, wherein the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are a first P-channel type MOS (PMOS) transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, respectively, wherein the first resistor is coupled to the first power rail and a first node, wherein gate, source, and drain of the first PMOS transistor are coupled to the first node, the first power rail, and the first gate line, respectively, wherein gate, drain, and source of the fourth NMOS transistor are coupled to the first branch voltage generated by branching the supply voltage, the first power rail, and a gate of the fifth NMOS transistor, respectively, wherein drain and source of the fifth NMOS transistor are coupled to the first branch voltage and the first gate line, respectively, wherein gate, drain, and source of the sixth NMOS transistor are coupled to the first gate line, the first node, and a drain of the seventh NMOS transistor, respectively, and wherein gate and source of the seventh NMOS transistor are coupled to the second gate line and the first capacitor, respectively. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838