DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10 and 17-20 in the reply filed on 07/06/2026 is acknowledged.
Status of the Application
Claims 1-10 and 17-26 remain pending in this application. Acknowledgement is made of the amendment received 07/06/2026. Claims 11-16 are canceled and claims 21-26 are added for consideration.
Claim Objections
Claim 18 objected to because of the following informalities:
Regarding claim 18, the claim recites “… the securing means is disposed directly over the top surface and the second contact means provided on the top surface of the top die”, it appears it should read “… the securing means is disposed directly over the top surface of the top die and the second means is provided on the top surface of the top die”, or “… the securing means is disposed directly over the top surface and the second means is provided on the top surface
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17, 18, 21, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomohiro (US 20160005696 A1, hereafter Tomohiro).
Regarding claim 17, Tomohiro discloses: An encapsulated semiconductor package (Tomohiro 1, fig 10, ¶0071-0074), comprising:
a substrate (Tomohiro 3, ¶0072) including a first contact means (Tomohiro 8, fig 1, ¶0072);
a plurality of stacked dies (Tomohiro 4, ¶0072, 0049) disposed over the substrate (Tomohiro fig 10, ¶0072), the plurality of stacked dies including:
a top die (Tomohiro 4, top 4 with regard to fig 10) positioned above the substrate (Tomohiro fig 10), the top die including:
a top surface (Tomohiro 4b, ¶0072, fig 10), and
a second contact means (Tomohiro 7, ¶0072) provided on the top surface (Tomohiro fig 10, ¶0072);
a connection means (Tomohiro 9, ¶0072) extending between and electrically connecting the second contact means of the top die and the first contact means of the substrate (Tomohiro fig 10, ¶0072, connects 7 and 8 , respectively);
a securing means (Tomohiro 10, ¶0037, 0041, at least capable thereof, 10 adheres 11 to 4, thereby securing 11 to 4, and further securing 9, ¶0055) disposed directly over the top die (Tomohiro fig 10, ¶0048, 0072), the securing means receiving and securing a portion of the connection means therein (Tomohiro ¶0055, “10 … is cured in a state in which it encloses portions of the bonding wires 9”); and
a protective means (Tomohiro 11, ¶0008, 0037, 0054, 0072, at least capable thereof, 11 reflects light to at least protect 4) disposed directly over the securing means (Tomohiro fig 10, ¶0072).
Regarding claim 18, Tomohiro discloses: The encapsulated semiconductor package of claim 17, wherein the securing means (Tomohiro 10) is disposed directly over the top surface (as best understood to mean “the top surface of the top die”)(Tomohiro 4b) and the second contact means (Tomohiro 7) provided on the top surface of the top die (Tomohiro fig 10, ¶0072).
Regarding claim 21, Tomohiro discloses: A semiconductor package (Tomohiro 1, fig 10, ¶0071-0074), comprising:
a substrate (Tomohiro 3, ¶0072) including a substrate contact (Tomohiro 8, fig 1, ¶0072);
a plurality of stacked dies (Tomohiro 4, ¶0072, 0049) disposed over the substrate (Tomohiro fig 10, ¶0072), the plurality of stacked dies including a top die (Tomohiro 4, top 4 with regard to fig 10) having a top surface (Tomohiro 4b, ¶0072, fig 10);
a die contact (Tomohiro 7, ¶0072) provided on the top surface of the top die (Tomohiro fig 10, ¶0072);
a bond wire (Tomohiro 9, ¶0072) extending between and electrically connecting the die contact and the substrate contact (Tomohiro fig 10, ¶0072, connects 8 and 7 , respectively), the bond wire including a first portion (Tomohiro 9, portion embedded in 10, ¶0037, 0066, fig 8d, 10) and a second portion (Tomohiro 9, portion embedded in 2, ¶0037, 0066, fig 8d, 10) formed adjacent the first portion (Tomohiro fig 10, ¶0037-0038, 0072, 9 forms a continuous wire between 8 and 7, therefore the first and second parts must be adjacent each other);
a multifunctional interface material (MIM) structure (Tomohiro 10, 11, fig 10, ¶0037, 0072, 10 and 11 form a structure having more than a single function (10 adheres 11 to 4 and secures and protects 9, ¶0037, 0041; 11 reflects light to protect 4, ¶0008, 0037, 0054), are at an interface (10 directly contacts 4b, fig 10), and contain an interface (between 10 and 11); therefore 10 and 11, under a broadest reasonable interpretation (BRI), comprise “a multifunctional interface material (MIM) structure”) disposed directly over the top surface of the top die (Tomohiro fig 10, ¶0048, 0072), wherein the first portion of the bond wire extends through and is secured within the MIM structure (Tomohiro ¶0037, 0055 “10 … is cured in a state in which it encloses portions of the bonding wires 9”); and
a molding compound (Tomohiro 2, ¶0049, “sealing resin (mold resin)”, ¶0072) disposed over the substrate and at least a portion of the plurality of stacked dies (Tomohiro fig 10, ¶0072), wherein the second portion of the bond wire extends through the molding compound (Tomohiro fig 10, ¶0037, 0038, 0072).
Regarding claim 24, Tomohiro, in at least one embodiment, discloses: The semiconductor package of claim 21, wherein the MIM structure (Tomohiro 10, 11) and the molding compound (Tomohiro 2) are in planar alignment and collectively form a top surface of the semiconductor package (Tomohiro fig 6, 10, ¶0059-0061, 0075).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro (US 20160005696 A1, hereafter Tomohiro) in view of Uchida et al (US 20200020669 A1, hereafter Uchida).
Regarding claim 1, Tomohiro teaches: A semiconductor package (Tomohiro 1, fig 10, ¶0071-0074), comprising:
a substrate (Tomohiro 3, ¶0072);
a plurality of stacked dies (Tomohiro 4, ¶0049, 0072) disposed over the substrate (Tomohiro fig 10, ¶0072), the plurality of stacked dies including:
a top die (Tomohiro 4, top 4 with regard to fig 10) positioned above the substrate (Tomohiro fig 10), the top die including:
a top surface (Tomohiro 4b, ¶0072, fig 10), and
a die contact (Tomohiro 7, ¶0072) formed on the top surface (Tomohiro fig 10, ¶0072);
a multifunctional interface material (MIM) structure (Tomohiro 10, 11, fig 10, ¶0037, 0072, 10 and 11 form a structure having more than a single function (10 adheres 11 to 4 and secures and protects 9, ¶0037, 0041; 11 reflects light to protect 4, ¶0008, 0037, 0054), are at an interface (10 directly contacts 4b, fig 10), and contain an interface (between 10 and 11); therefore 10 and 11, under a broadest reasonable interpretation (BRI), comprise “a multifunctional interface material (MIM) structure”) disposed over the top die (Tomohiro fig 10, ¶0048, 0072), the MIM structure including:
an adhesive layer (Tomohiro 10, ¶0037, 0072) disposed directly over the top surface of the top die (Tomohiro fig 10, ¶0048, 0072); and
a bond wire (Tomohiro 9, ¶0072) contacting the die contact of the top die (Tomohiro fig 10, ¶0037-0038, 0072), wherein at least a portion of the bond wire extends through the adhesive layer of the MIM structure (Tomohiro 9, portion embedded in 10, ¶0037, 0066, fig 8d, 10).
Tomohiro does not teach: the MIM structure further including a polymer layer disposed directly over the adhesive layer.
Uchida, in the same field of endeavor of semiconductor device manufacturing, teaches: an adhesive layer (Uchida 91, ¶0076) disposed directly over a top surface of a top die (Uchida 70, ¶0076); and
a polymer layer (Uchida 95, ¶0024, 0076, “epoxy resin composition having an epoxy resin as a primary component and containing a phenol resin and a silica filler”) disposed directly over the adhesive layer (Uchida fig 9, ¶0076).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the MIM structure of Tomohiro such that the mirrored chip is substituted by the polymer layer of Uchida, and such that is it directly over the adhesive layer, as taught by Uchida, in order to absorb shock of the laser light and protect the underlying chips (Uchida ¶0078).
Regarding claim 2, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1, wherein the at least the portion of the bond wire (Tomohiro 9, portion embedded in 10) is secured within the adhesive layer (Tomohiro 10) of the MIM structure (Tomohiro 10 as modified to include Uchida 95)(Tomohiro ¶0037, 0055 “10 … is cured in a state in which it encloses portions of the bonding wires 9”).
Regarding claim 3, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1, further comprising:
a molding compound (Tomohiro 2, ¶0049, “sealing resin (mold resin)”, ¶0072) disposed over the substrate (Tomohiro 3) and at least a portion of the plurality of stacked dies (Tomohiro 4)(Tomohiro fig 10, ¶0072), the molding compound formed adjacent to:
the top surface of the top die (Tomohiro 4b)(Tomohiro fig 6, 10, ¶0059-0061, 0072), and
the MIM structure (Tomohiro 10 as modified to include Uchida 95)(Tomohiro fig 6, 10, ¶0059-0061, 0072).
Regarding claim 4, Tomohiro in view of Uchida teaches: The semiconductor package of claim 3, wherein the bond wire (Tomohiro 9) further includes another portion disposed within and extending through the molding compound (Tomohiro 2)(Tomohiro 9, portion embedded in 2, ¶0037, 0066, fig 8d, 10).
Regarding claim 5, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1, wherein the MIM structure (Tomohiro 10 as modified to include Uchida 95) further includes an additive (Uchida ¶0024, 0025, “silica filler”) disposed within at least one of the adhesive layer (Tomohiro 10) or the polymer layer (Tomohiro as modified to include Uchida 95)(Uchida ¶0024, 0025, 0076, 95 comprising same materials as 50).
Regarding claim 6, Tomohiro in view of Uchida teaches: The semiconductor package of claim 5, wherein the additive (Uchida ¶0024, 0025, “silica filler”) is disposed in the polymer layer (Tomohiro as modified to include Uchida 95) of the MIM structure (Tomohiro 10 as modified to include Uchida 95)(Uchida ¶0024, 0025).
Tomohiro in view of Uchida does not explicitly teach: wherein the additive is disposed in the adhesive layer of the MIM structure.
Uchida further teaches: an additive (Uchida ¶0024, 0025, “silica filler”) disposed within an adhesive layer (Uchida 40, ¶0025, 0044)(Uchida ¶0025, 0044).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the adhesive layer of Tomohiro in view of Uchida to include an additive, as taught by Uchida, and such that “the additive is disposed in the adhesive layer and the polymer layer of the MIM structure”, in order to provide an adhesive that reflows without melting another layer (Uchida ¶0025).
Regarding claim 8, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1.
Tomohiro in view of Uchida does not explicitly teach: wherein the adhesive layer of the MIM structure includes an epoxy resin.
Uchida, in at least one embodiment, further teaches: an adhesive layer (Uchida 40, ¶0025, 0044) includes an epoxy resin (Uchida ¶0025, “an epoxy resin”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the adhesive layer of Tomohiro in view of Uchida to include an epoxy resin, as taught by Uchida, and such that “he adhesive layer of the MIM structure includes an epoxy resin”, in order to provide an adhesive that reflows without melting another layer (Uchida ¶0025).
Regarding claim 9, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1.
Tomohiro in view of Uchida does not explicitly teach: wherein the adhesive layer of the MIM structure includes a height between approximately 20 micrometers (µm) to approximately 30 µm.
Tomohiro further teaches: adjusting a thickness of an adhesive layer (Tomohiro 10)(Tomohiro ¶0062, 0075).
Uchida further teaches: an adhesive layer (Uchida 40, ¶0025, 0044) includes a height between 5 and 150 µm (Uchida ¶0025).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the height of the adhesive layer of Tomohiro in view of Uchida to be between approximately 20 µm to approximately 30 µm, in order to embed a portion of the bond wire within the adhesive layer while keeping a total thickness small, thereby reducing a total thickness of the package (Tomohiro ¶0056, 0062, Uchida ¶0025).
Further, the adjustment of thickness of an adhesive layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness of an adhesive layer is disclosed by Tomohiro and Uchida, and therefore discovering the optimum or working range of "the adhesive layer of the MIM structure includes a height between approximately 20 micrometers (µm) to approximately 30 µm" involves only routine skill in the art.
Regarding claim 10, Tomohiro in view of Uchida teaches: The semiconductor package of claim 1.
Tomohiro in view of Uchida does not explicitly teach: wherein the polymer layer of the MIM structure includes a height between approximately 10 µm to approximately 20 µm.
Tomohiro further teaches: adjusting a thickness of an MIM structure layer (Tomohiro 10, 11)(Tomohiro ¶0040, 0061, 0075).
Uchida further teaches: a polymer layer (Uchida 50, ¶0076) includes a height between 5 and 300 µm (Uchida ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the height of the polymer layer of Tomohiro in view of Uchida to be between approximately 10 µm to approximately 20 µm, in order to protect the top die (Uchida ¶0056, 0078) while keeping a total thickness small, thereby reducing a total thickness of the package (Tomohiro ¶0061-0062, Uchida ¶0025).
Further, the adjustment of thickness of an polymer layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness of an polymer layer is disclosed by Tomohiro and Uchida, and therefore discovering the optimum or working range of "the adhesive layer of the MIM structure includes a height between approximately 20 micrometers (µm) to approximately 30 µm" involves only routine skill in the art.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro (US 20160005696 A1, hereafter Tomohiro) in view of Uchida et al (US 20200020669 A1, hereafter Uchida), as applied to claim 5 above, and further in view of Huang et al (US 20200075527 A1, hereafter Huang).
Regarding claim 7, Tomohiro in view of Uchida teaches: The semiconductor package of claim 5.
Tomohiro in view of Uchida does not explicitly teach: wherein the additive of the MIM structure includes at least one of aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, or diamond powder.
Huang, in the same field of endeavor of semiconductor device manufacturing, teaches: an additive (Huang ¶0059, under a BRI of “additive”) disposed within an adhesive layer (Huang 135, ¶0059, “adhesive material 135”) includes at least one of aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, or diamond powder (Huang ¶0059, “aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, diamond powder”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the additive of the MIM structure of Tomohiro in view of Uchida, to include at least one of aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, or diamond powder, as taught by Huang, in order to improve the thermal conductivity of the MIM structure (Huang ¶0059).
Claims 19, 22, 23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro (US 20160005696 A1, hereafter Tomohiro), as applied to claims 17 or 21 above, and further in view of Uchida et al (US 20200020669 A1, hereafter Uchida).
Regarding claim 19, Tomohiro teaches: The encapsulated semiconductor package of claim 17.
Tomohiro does not teach: wherein at least one of the securing means or the protective means further includes additive means for adjusting operational characteristics of the at least one of the securing means or the protective means.
Uchida, in the same field of endeavor of semiconductor device manufacturing, teaches: at least one of a securing means (Uchida 40, 91, ¶0025, 0044, 0076, at least capable thereof, 40/91 adheres 50/95 to 30/70, thereby securing 40/95 to 30/70 respectively) or a protective means (Uchida 50, 95, ¶0024, 0078, at least capable thereof, 50/95 at least protect 30/70 respectively) further includes additive means (Uchida ¶0024, 0025, “silica filler”) for adjusting operational characteristics of the at least one of the securing means or the protective means (Uchida ¶0024-0025, 0044, 0056, adjusting elastic modulus, thermal expansion coefficient, glass transition temperature, stiffness, ¶0076).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the securing means and/or the protective means of Tomohiro to include an additive, as taught by Uchida, and such that “at least one of the securing means or the protective means further includes additive means for adjusting operational characteristics of the at least one of the securing means or the protective means”, in order to provide an adhesive that reflows without meting another layer (Uchida ¶0025), and/or in order to protect an underlying chip (Uchida ¶0078).
Regarding claim 22, Tomohiro teaches: The semiconductor package of claim 21, wherein the MIM structure (Tomohiro 10, 11) includes an adhesive layer (Tomohiro 10, ¶0037, 0072) disposed directly over the top surface of the top die (Tomohiro 4b), and wherein the first portion of the bond wire (Tomohiro 9, portion embedded in 10) extends through and is secured within the adhesive layer (Tomohiro fig 10, ¶0037, 0055 “10 … is cured in a state in which it encloses portions of the bonding wires 9”).
Tomohiro does not teach: the MIM structure further comprises a polymer layer disposed directly over the adhesive layer.
Uchida, in the same field of endeavor of semiconductor device manufacturing, teaches: an adhesive layer (Uchida 91, ¶0076) disposed directly over a top surface of a top die (Uchida 70, ¶0076); and
a polymer layer (Uchida 95, ¶0024, 0076, “epoxy resin composition having an epoxy resin as a primary component and containing a phenol resin and a silica filler”) disposed directly over the adhesive layer (Uchida fig 9, ¶0076).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the MIM structure of Tomohiro such that the mirrored chip is substituted by the polymer layer of Uchida, and such that is it directly over the adhesive layer, as taught by Uchida, in order to absorb shock of the laser light and protect the underlying chips (Uchida ¶0078).
Regarding claim 23, Tomohiro in view of Uchida teaches: The semiconductor package of claim 22, wherein the polymer layer (Tomohiro as modified to include Uchida 95, similar to Tomohiro 11) of the MIM structure (Tomohiro 10 as modified to include Uchida 95) provides a compressive force (Tomohiro ¶0048, Uchida ¶0044) on the adhesive layer (Tomohiro 10, similar to Uchida 91) to secure the first portion of the bond wire (Tomohiro 9, portion embedded in 10) within the adhesive layer (Tomohiro ¶0055, “10 … is cured in a state in which it encloses portions of the bonding wires 9”)(this functional limitation does not distinguish the claimed package over the prior art, since it appears that this limitation can be performed by the prior art structure of Tomohiro in view of Uchida; a polymer layer disposed directly on the adhesive layer in which the bond wire is embedded. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function, see MPEP 2112.01, 2114).
Regarding claim 25, Tomohiro teaches: The semiconductor package of claim 21.
Tomohiro does not explicitly teach: wherein the MIM structure includes an overall height between approximately 30 micrometers (µm) to approximately 50 µm.
Tomohiro further teaches: adjusting a thickness of an MIM structure layer (Tomohiro 10, 11)(Tomohiro ¶0040, 0061, 0075), and adjusting a thickness of the adhesive layer of the MIM structure (Tomohiro 10)(Tomohiro ¶0062, 0075).
Uchida, in the same field of endeavor of semiconductor device manufacturing, teaches: an adhesive layer (Uchida 40, ¶0025, 0044) includes a height between 5 and 150 µm (Uchida ¶0025); and
a another layer (Uchida 50, ¶0076) includes a height between 5 and 300 µm (Uchida ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a thickness of the MIM structure of Tomohiro by adjusting either or both of the layers of the MIM structure of Tomohiro, as taught by Uchida, and such that “the MIM structure includes an overall height between approximately 30 micrometers (µm) to approximately 50 µm”, in order to embed a portion of a bond wire within the adhesive to protect and secure it (Tomohiro ¶0008, 0037, 0054), and/or to protect the top die (Uchida ¶0056, 0078), while keeping a total thickness small, thereby reducing a total thickness of the package (Tomohiro ¶0056, 0062, Uchida ¶0025).
Further, the adjustment of thickness of an adhesive layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness of an adhesive layer is disclosed by Tomohiro and Uchida, and therefore discovering the optimum or working range of "the MIM structure includes an overall height between approximately 30 micrometers (µm) to approximately 50 µm" involves only routine skill in the art.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro (US 20160005696 A1, hereafter Tomohiro), as applied to claim 17 above, and further in view of Xu et al (US 20190103409 A1, hereafter Xu).
Regarding claim 20, Tomohiro teaches: The encapsulated semiconductor package of claim 17, further comprising:
a distinct connection means (Tomohiro 9, a lower 9 connecting lower 4, fig 10, ¶0072) and a fourth contact means (Tomohiro 7, on an upper surface of lower 4, fig 10, ¶0072) provided on a stacked die (Tomohiro 4, lower 4, fig 10, ¶0072) of the plurality of stacked dies (Tomohiro 4) positioned adjacent to and below the top die (Tomohiro fig 10, ¶0072).
Tomohiro does not teach: a distinct connection means extending between and electrically connecting a third contact means provided on the top die; and
wherein the securing means receives and secures a portion of the distinct connection means.
Xu, in the same field of endeavor of semiconductor device manufacturing, teaches:
a distinct connection means (Xu 102, ¶0031, 0034) extending between and electrically connecting a third contact means (Xu 108, of the top most 103, fig 1A, ¶0041)(Xu fig 1A, ¶0034) provided on a top die (Xu 103, top most 103, fig 1A) and a fourth contact means (Xu 108, of a die below the top 103, fig 1A, ¶0041) provided on a stacked die (Xu 103, top most 103, fig 1A) of a plurality of stacked dies (Xu 101, fig 1A, ¶0031) positioned adjacent to and below the top die (Xu fig 1A, ¶0031, 0041),
wherein a securing means (Xu 104, ¶0031) receives and secures a portion of the distinct connection means (Xu fig 1A, ¶0037).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Tomohiro to include the distinct connection means and third contact of Xu, such that “a distinct connection means extending between and electrically connecting a third contact means provided on the top die and a fourth contact means provided on a stacked die of the plurality of stacked dies positioned adjacent to and below the top die”, and such that “the securing means receives and secures a portion of the distinct connection means”, as taught by Xu, in order to shorten a die to die signal path, thereby improving data rates between dies and/or reducing latency of a signal (Xu ¶0045, Tomohiro ¶0073).
Examiner’s note: it appears that there are typos within at least ¶0034 of the specification of Xu in which numerical identifiers are mis-referenced, however, as best understood, and with reference to fig 1A and ¶0031, it appears the designations are as follows: die stack 101, wires 102, adjacent dies 103.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro (US 20160005696 A1, hereafter Tomohiro), as applied to claim 21 above, and further in view of Arai et al (US 20210082878 A1, hereafter Arai).
Regarding claim 26, Tomohiro teaches: The semiconductor package of claim 21.
Tomohiro does not teach: wherein the MIM structure is disposed directly over only a portion of the top surface of the top die, and wherein the molding compound covers a remaining portion of the top surface of the top die.
Arai, in the same field of endeavor of semiconductor device manufacturing, teaches: a MIM structure (Arai 4a, 3c, fig 1, 5C, ¶0019, 0020) is disposed directly over only a portion of a top surface of a top die (Arai 3b, ¶0019)(Arai fig 5C, ¶0039), and wherein a molding compound (Arai 6a, 7, ¶0035, 0039) covers a remaining portion of the top surface of the top die (Arai fig 5C, 5J, ¶0032, 0046).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the MIM structure of Tomohiro such that is shifted such that it is “disposed directly over only a portion of the top surface of the top die, and wherein the molding compound covers a remaining portion of the top surface of the top die”, as taught by Arai, in order to reduce inter die thickness by offsetting the MIM and top die, thereby eliminating wire embedding were not needed (Arai ¶0028), and/or in order to reduce warpage (Arai ¶0028).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
St. Amand et al (US 8072083 B1) is cited as an example of an analogous device further comprising a polymer film disposed over an adhesive film containing a bond wire.
Sano et al (US 20210288018 A1) is cited as an example of an analogous device further comprising a bond wire connecting stacked chips and a substrate.
Chen et al (US 20160307872 A1) is cited as an example of an analogous device further a polymer molding material with additives.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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