DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on April 1, 2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
Claims 4, 7, 9-10, and 13-18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Regarding Claim 4 and the substantially similar limitations of claims 7, 9-10, and 13-18: Claim references ‘a bit at a predetermined position.” All bits in a memory array are assigned to a predetermined position. It is unclear from the language of the claim what is intended by this limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 7,545,673 B2 to Menahem Lasser (hereafter Lasser).
Regarding Independent Claim 1, Lasser discloses a memory device comprising:
a plurality of memory cells (An array of memory cells 22: Lasser, Figure 1 and col.5:51); and
a peripheral unit (Controller 34 and Managing Circuit 28: Lasser, Figure 1) configured to store k bits in each of the memory cells (Managing Circuit 28 configured to set all bits in a page to a specific value: Lasser, col.6:36-38)
by controlling the memory cells to form 2k-1+1 threshold voltage distributions (Programming each cell to reduced density per cell: Lasser, col.4:37-39),
wherein k is an integer (Example given is two bits per cell, 2--2, or one bit per cell, 21: Lasser, col.4:36-39).
Regarding Claim 2, Lasser discloses the memory device according to claim 1, wherein
a plurality of first memory cells (First set of memory cells: Lasser, Figure 2B),
among the plurality of memory cells,
form remaining threshold voltage distributions (Storing remaining data after eliminating certain data states: Lasser, col.4:42-44),
which are the 2k-1+1 threshold voltage distributions excluding a second lowest threshold voltage distribution (Excluded, dummy, cells may include the second lowest bit: Lasser, col.5:36-40), and
a plurality of second memory cells,
among the plurality of memory cells (When storing data at lesser density, the unprogrammed data will inherently be allocated to additional cells),
form remaining threshold voltage distributions (Storing remaining data after eliminating certain data states: Lasser, col.4:42-44),
which are the 2k-1+1 threshold voltage distributions excluding a lowest threshold voltage distribution (Optionally excluding the lowest threshold voltage instead of the second lowest threshold voltage: Lasser, col. 5:40-42).
Regarding Claim 3, Lasser discloses the memory device according to claim 2, wherein
each of the plurality of first memory cells is located in any one of the remaining threshold voltage distributions (Programming the memory cells at a lesser density: Lasser, Figure 2B),
which are the 2k-1+1 threshold voltage distributions (Where the lesser density allows for a subset of the full data: Lasser, Figure 2B)
excluding the second lowest threshold voltage distribution (Wherein the dummy data may include the second lowest threshold: Lasser, col.5:36-40),
according to remaining bits, which are the k bits excluding a bit at a predetermined position (Where the programmed cells represent the remaining bits after excluding the predetermined bit: Lasser, Figure 2B).
Regarding Claim 4 and the substantially similar limitations of Claim 19, Lasser discloses the memory device according to claim 2, wherein
each of the plurality of second memory cells is located in any one of the remaining threshold voltage distributions (Programming the memory cells at a lesser density: Lasser, Figure 2B),
which are the 2k-1+1 threshold voltage distributions excluding the lowest threshold voltage distribution (The data distributions excluding the lowest threshold voltage distribution: Lasser, Figure 2),
according to remaining bits, which are the k bits excluding a bit at a predetermined position (Where the programmed cells represent the remaining bits after excluding the predetermined bit: Lasser, Figure 2B).
Regarding Claim 5, Lasser discloses the memory device according to claim 2, wherein
the first memory cells are even-numbered memory cells, and wherein the second memory cells are odd-numbered memory cells (When eliminating one bit of data while storing at reduced density, the programming operation will inherently enter an even/odd sequence, with an even cell storing the first set of data states and the odd cells storing the remaining data states, or vice versa: Lasser, col.4:21-26).
Regarding Claim 6, Lasser discloses the memory device according to claim 2, wherein
the first memory cells are the odd-numbered memory cells, and wherein the second memory cells are the even-numbered memory cells (When eliminating one bit of data while storing at reduced density, the programming operation will inherently enter an even/odd sequence, with an even cell storing the first set of data states and the odd cells storing the remaining data states, or vice versa: Lasser, col.4:21-26).
Regarding Claim 7, Lasser discloses the memory device according to claim 2, wherein
a bit at a predetermined position, among the k bits to be stored in each of the plurality of first memory cells, is an erase value (The data distributions excluding the lowest threshold voltage distribution, illustrated as 11 or the erase value: Lasser, Figure 2), and
a bit at the predetermined position, among the k bits to be stored in each of the plurality of second memory cells, is a complement of the erase value (Wherein the dummy data may include the second lowest threshold: Lasser, col.5:36-40).
Regarding Claim 8 and the substantially similar limitations of Claim 20, Lasser discloses the memory device according to claim 1, wherein
the peripheral unit is configured to read data (Controller 34 managing read operations: Lasser, col.6:56-57)
stored in the plurality of memory cells based on 2k-1 read voltages (Based on a low density storage configuration: Lasser, col.6:56-59),
each located between respective threshold voltage distributions (The read voltages applied laying between expected voltage distributions: Lasser, Figures 2A and 2B).
Regarding Claim 9 and the substantially similar limitations of Claim 16, Lasser discloses the memory device according to claim 8, wherein
the plurality of memory cells includes a plurality of first memory cells (First set of memory cells: Lasser, Figure 2B) and a plurality of second memory cells (Memory cells not included in the first set: Lasser, Figure 2A), and
wherein the peripheral unit is configured to
apply a lowest read voltage, among the 2k-1read voltages, to the memory cells and configured to read a bit at a predetermined position (Reading both the ignored memory states and/or the active data: Lasser, col.6:56-59),
among the k bits stored in each of the plurality of second memory cells, among the plurality of memory cells (Among the many memory states: Lasser, Figure 2A),
according to a result of comparing a threshold voltage of each of the plurality of second memory cells with the lowest read voltage (Reading the various data levels from the appropriate threshold voltages: Lasser, col.6:50-55).
Regarding Claim 10 and the substantially similar limitations of Claim 17, Lasser discloses the memory device according to claim 9, wherein,
regardless of a result of applying any of the 2k-1 read voltages to the memory cells (An event taking place without consideration of other events does not identify a positive limitation),
the peripheral unit is configured to read, as an erase value, a bit at the predetermined position (The erased position being the lowest available data state: Lasser, col.4:57-58),
among the k bits stored in each of the plurality of first memory cells, among the plurality of memory cells (Among the many memory states: Lasser, Figure 2A).
Regarding Independent Claim 11, Lasser discloses a memory device comprising:
a plurality of memory cells (An array of memory cells 22: Lasser, Figure 1 and col.5:51); and
a peripheral unit (Controller 34 and Managing Circuit 28: Lasser, Figure 1)
configured to control the plurality of memory cells to form n number of threshold voltage distributions (Disclosing four data states when MLC stores two bits: Lasser, Figure 2A)
when k bits are stored in each of the plurality of memory cells during a normal program operation (Four data states corresponding to two bits of data: Lasser, col.3:40-42) and
configured to control the plurality of memory cells to form m number of threshold voltage distributions when k bits are stored in each of the plurality of memory cells (Threshold voltages located between data distributions: Lasser, col.4:65-67)
during a fast program operation (During a low density program operation: Lasser, col.5:50-54; Note: Programming to fewer data states will inherently be faster than programming to more data states),
wherein n is greater than m (Requiring three voltage thresholds, Vra – Vrc, to differentiate between four data states: Lasser, col.4:65-67), and
wherein k, n, and m are integers (Two bits, four data states, and three voltage thresholds: Lasser, Figure 2A and col.4:65-67).
Regarding Claim 12, Lasser discloses the memory device according to claim 11, wherein,
in the fast program operation (During a low density program operation: Lasser, col.5:50-54),
when the k bits to be stored in a memory cell, among the plurality of memory cells, are erase values (Programming an erase state: Lasser, col.5:58-60),
the peripheral unit is configured to control the memory cell (Controller 34: Lasser, Figure 1) to be located in a lowest threshold voltage distribution (The erase state being the lowest threshold: Lasser, col.4:57),
among the m threshold voltage distributions (The erase state, 11, being lowest state among all the data states: Lasser, Figure 2A).
Regarding Claim 13, Lasser discloses the memory device according to claim 11, wherein,
in the fast program operation (During a low density program operation: Lasser, col.5:50-54),
when a bit at a predetermined position, among the k bits to be stored in a memory cell, among the plurality of memory cells, is a complement of an erase value (Showing the predetermined position LSB to be 0, a complement to the erase value of 1: Lasser, Figure 2A) and
remaining bits, which are the k bits excluding the bit at the predetermined position, are erase values (When the remaining bits other than the LSB are erase values, in this instance position A with a value of 10: Lasser, Figure 2B),
the peripheral unit is configured to control the memory cell to be located in a second lowest threshold voltage distribution, among the m threshold voltage distributions (The data state in this condition, 10, is the second lowest of the threshold voltage distributions: Lasser, Figure 2B).
Regarding Claim 14, Lasser discloses the memory device according to claim 11, wherein,
in the fast program operation (During a low density program operation: Lasser, col.5:50-54),
when at least one of remaining bits to be stored in a memory cell, among the plurality of memory cells, which are the k bits excluding a bit at a predetermined position, is a complement of an erase value (When the remaining bits other than the LSB are complement to erase values, in this instance position C with a value of 00: Lasser, Figure 2B),
the peripheral unit is configured to control the memory cell to be located in any of the m threshold voltage distributions excluding a lowest threshold voltage distribution and a second lowest threshold voltage distribution according to the remaining bits (The data state in this condition, 00, excludes the lowest and the second lowest of the threshold voltage distributions: Lasser, Figure 2B).
Regarding Claim 15, Lasser discloses the memory device according to claim 11, wherein
a bit at a predetermined position, among the k bits to be stored in each of a plurality of first memory cells, among the plurality of memory cells, is an erase value (A bit at the predetermined position, in this instance LSB, being 1: Lasser, Figure 2A), and
wherein a bit at the predetermined position, among the k bits to be stored in each of a plurality of second memory cells, among the plurality of memory cells, is a complement of the erase value (Although not illustrated in isolation by a figure, position 01 corresponds to data state B: Lasser, Figure 2A)
Regarding Independent Claim 18, Lasser discloses a storage device comprising:
a controller configured to convert first data into second data (Controller 34 breaks the data into one of two formats: Lasser, col.6:4-5 and Figure 1),
the controller converting, in the first data, a bit at a predetermined position among k bits corresponding to each of a plurality of even-numbered memory cells (When eliminating one bit of data while storing at reduced density, the programming operation will inherently enter an even/odd sequence, with an even cell storing the first set of data states and the odd cells storing the remaining data states, or vice versa: Lasser, col.4:21-26), among a plurality of target memory cells, into a first value and converting a bit at the predetermined position among k bits corresponding to each of a plurality of odd-numbered memory cells, (When storing data at lesser density, the unprogrammed data will inherently be allocated to additional cells) among the plurality of target memory cells, into a second value, the second value being different from the first value (Controller 34 configured to store data stored in cells in either two-bit or single bit data format: Lasser, col.4:36-39); and
a memory device configured to store the second data in the plurality of target memory cells under the control of the controller (Controller 34 writing the data to the memory cells: Lasser, col.6:20-22),
wherein k is an integer (Example given is two bits per cell, 2--2, or one bit per cell, 21: Lasser, col.4:36-39).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20120290768 A1 to Amit Rubowitz: Teaching divided programming operations where LSB and MSB data are programmed independently.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 01/21/2026