DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11 - 12 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Song et al. (US 20250024691) herein referred to as Song. Fig. 2
As to claim 1, an apparatus comprising:
a semiconductor substrate in a first layer ([0048] Fig. 2, “An upper dielectric layer 200 is disposed on the pad dielectric layer 150 and the stack structure ST. “, Song), the semiconductor substrate being divided, at least in part, into a memory cell array region, ([0049] Fig. 2, “On the cell array region CAR”, Song), a peripheral circuit region ([0038] The circuit layers constitute a peripheral circuit that drive memory cells) and a contact plug region ([0049] “On the contact region CCR, cell contact plugs CCP are disposed that penetrate the upper dielectric layer 200 and the pad dielectric layer 150 and connect with the word lines WL.”, Song ) between the memory cell array region (CAR) and the peripheral circuit region;
a plurality of word lines (Fig. 2, WL, Song) embedded in the semiconductor substrate (Fig. 2, 200, Song), the plurality of word lines extending in parallel across only the memory cell array region (Fig. 2, CAR, Song) and the contact plug region (Fig. 2, CCR, Song);
a first nitride film in a second layer ([0047] 150, “The pad dielectric layer 150 may include one dielectric layer or a plurality of stacked dielectric layers. The dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.”, Song) above the first layer ([0048] 200, “The upper dielectric layer 200 includes, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.”),
the first nitride film (Fig. 2, 150, Song) covering the memory cell array region (Fig. 2, CAR, Song) and the contact plug region (Fig. 2, CCR, Song) of the semiconductor substrate (Fig. 2, 200, Song);
a first oxide film in the second layer ([0047] Fig. 2 , 150, Song), the first oxide film covering the peripheral circuit region ([0038] Fig. 2 peripheral circuit region not shown, Song) and
a plurality of contact plugs ([0049] “The cell contact plugs CCP are spaced apart from each other in the first direction D1.”, Song) in the first nitride film ([0047] Fig. 2, 150, Song) above the contact plug region (Fig. 2, CCR, Song) of the semiconductor substrate (Fig. 2, 200, Song) to be connected to the plurality of word lines (Fig. 2, WL, Song), respectively.
As to claim 11, the apparatus of claim 1, wherein
each of the plurality of word lines (Fig. 2, WL, Song) has a lower section contacting a STI region (See Annotated Song Fig. 2 below. ILD is functioning as an STI region, Fig. 5 first hole H1 [0064]” In addition, the formation of the word lines WL includes forming a trench that penetrates the mold structure MS,” Song) and an upper section contacting the first nitride film in the contact plus region.
As to claim 12,an apparatus comprising:
a plurality of word lines (Fig. 2, WL, Song) embedded in a semiconductor substrate ([0048] Fig. 2, 200 Song) the plurality of word lines being arranged in a first direction,
each of the plurality of word lines extending in a second direction (Fig. 2, word lines are stacked in a second direction, Song);
a first nitride film (Fig. 2, 150 Song) covering the plurality of word lines (Fig. 2 WL, Song) and
a plurality of contact plugs (Fig. 2 CCP, Song) penetrating through the first nitride film (Fig. 2 150, Song) so as to contact the plurality of word lines (Fig. 2 WL, Song), respectively, wherein
each of the plurality of word lines (Fig. 2 WL, Song) has a lower section covered with a STI region in the first direction (Annotated word line, Song Fig. 2) and an upper section covered with the first nitride film (Fig. 2, 150 Song) in the first direction.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 - 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20250024691) herein referred to as Song,
As to claim 13, Song discloses the elements of the apparatus of claim 12, as discussed above, further comprising
a MOS transistor (obvious) having a gate electrode (Fig. 13 [0038], [0080] circuit layers are located within (110); circuit layer includes CMOS, Manning), wherein
a top surface of the gate electrode (Annotated gate electrode area, Song Fig. 2) is covered with a gate cap insulator ([0035] Fig. 2, layer 150 as first nitride covers layer 110 functioning as a cap insulator, Song) constituted by the first nitride film (Fig. 2, 150, Song).
Song does not appear to expressly disclose the limitations of claim 13. However, [0038] of the Song reference discloses circuit layers. Circuits rely on transistors to control and conduct electricity. A voltage applied to the gate electrode (obvious) creates an electric field that allows current to flow between the source and drain. It is well known in the art that circuit layers include CMOS (Complementary Metal-Oxide-Semiconductor), which are not an individual component, but rather the entire structural foundation of the chip built directly into the core semiconductor layers.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the device of Song, though not explicitly stated, includes the limitations of claim 13, a MOS transistor having a gate electrode, so as to produce a functioning semiconducting electrical device.
As to claim 14, Song discloses the elements of the apparatus of claim 13, further comprising
a second nitride film (Annotated Song Fig. 2, 2nd nitride film) arranged above the first nitride film (Annotated Song Fig. 2, 1st nitride film)., wherein
the each of the plurality of contact plugs (contact plugs CCP, Song) has a lower section contacting the upper section of an associated one of the plurality of word lines (Annotated Song Fig. 2, word line upper section) and surrounded by the first nitride film (Annotated Song Fig. 2, 1st nitride film) and an upper section surrounded by the second nitride film (Annotated 2nd nitride film, Manning).
As to claim 15, Song discloses the elements of the apparatus of claim 14, further comprising wherein
the lower section of each of the plurality of contact plugs (Fig. 2, CCP) is free from contacting with an oxide film (ILD can be made of silicon nitride [0035] “The base dielectric layer 110 and the interlayer dielectric layers ILD include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.”)
As to claim 16, Song discloses the elements of the apparatus of claim 14, further comprising
a third nitride film arranged between the first and second nitride films, (Annotated 1st , 2nd and 3rd nitride film, Song)
Song does not appear to expressly disclose: “the third nitride film is thinner (obvious) than each of the first and second nitride films.” Nitride films of different thickness are used in memory devices to engineer electric fields, control charge-trapping efficiency, and balance data retention against programming speed. However, engineering a specific thickness for the multi-layer (150) is not done perfectly. A tolerance is the acceptable, permissible range of variation for a physical dimension, resulting in one thickness being thinner or thicker than another.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the third nitride film may be thinner in thickness than each of the first and second nitride films since
Allowable Subject Matter
Claim 20 is allowed. The following is an examiner's statement of reasons for allowance: The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. The closest prior art is Song et al. (US 20250024691) herein referred to as Song, which teaches an analogous combined device.
As to claim 20, Song discloses the elements of a method as discussed above, comprising:
forming a plurality of word lines (Fig. 2, WL, Song) so as to be embedded in a semiconductor substrate ([0048] Fig. 2, “An upper dielectric layer 200 is disposed on the pad dielectric layer 150 and the stack structure ST. “, Song),;
forming a metal film ([0039] The word lines WL and the bit lines BL include, for example, at least one of a doped semiconductor, such as doped silicon, a metal, such as tungsten, copper, or aluminum, a conductive metal nitride, such as titanium nitride or tantalum nitride, or a transition metal, such as titanium or tantalum, Song ) covering the plurality of word lines (Fig. 2, WL, Song) with an insulating film interposed therebetween ;
forming a second nitride film (Annotated 2nd nitride film, Song) covering the first nitride film (Fig. 2, 150, Song) and the first oxide film (Annotated Song Fig. 2); and
forming a plurality of contact plugs (Fig. 2, CCR, Song) penetrating through the first (Fig. 2, 150, Song) and second nitride film (Annotated 2nd nitride film, Song) to contact the end portions of the plurality of word lines (Fig. 2, WL, Song), respectively.
Song does not disclose:
selectively removing the metal film covering an end portion of each of the plurality of word lines so as to expose the insulating film forming a first nitride film after the removing;
forming a first oxide film after the forming the first nitride film;
The remaining claims 2-10, 17-19, and 21 are allowable at least because it depends from allowable independent claims 1, 13 and 20 respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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