DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in this application. This is a second nonfinal rejection due to an inadvertent error on the part of the Examiner.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4 and 11-12 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Yanagisawa et al. (US Patent No 6,509,630, previously cited) hereinafter referred to as Yanagisawa.
Per Claim 1 Yanagisawa discloses a semiconductor package device, (see figures 1 and 4-5) comprising
a film substrate (10) comprising a sprocket hole (12);
a semiconductor chip (60) on the film substrate;
interconnection lines (22) connected to the semiconductor chip;
a dummy pattern (40) between the sprocket hole (12) and the semiconductor chip; and
a cutting pattern (44) between the semiconductor chip and the dummy pattern,
wherein the cutting pattern is spaced apart from the interconnection lines and the dummy pattern in a first direction (see figures 1 and 4-5)
Per Claim 4 Yanagisawa discloses the device of claim 1, (see figures 1 and 4-5) including a protective layer (62) on the interconnection lines, the dummy pattern and the cutting pattern. (see figure 4)
Per Claim 11 Yanagisawa discloses the device of claim 1, (see figures 1 and 4-5) including where the semiconductor chip comprises a plurality of semiconductor chips. (described in column 9 lines 60-64)
Per Claim 12 Yanagisawa discloses the device of claim 1, (see figures 1 and 4-5) including where the film substrate comprises a plurality of layers. (see column 8 lines 56-60)
Allowable Subject Matter
Claims 2-3, 5-10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance. No prior art was found that neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination.
The closest prior art appears to be Oh (previously cited) which teaches an analogous device including discloses a semiconductor package device, (see figure 1) comprising a film substrate (10) comprising a sprocket hole (12); a semiconductor chip (60) on the film substrate; interconnection lines (22) connected to the semiconductor chip; a cutting pattern (44) (see fig. 1)
Oh does not specifically disclose or suggest the element/step of “and a cutting pattern on the film substrate and spaced apart from the interconnection lines in a first direction, wherein a side surface of the cutting pattern is coplanar with a side surface of the film substrate, and wherein the interconnection lines and the cutting pattern comprise same material”, as recited by independent claim 14, in combination with the other elements/steps of the claim. No prior art was found that taught this novel method/device.
Oh does not specifically disclose or suggest the element/step of “a circuit substrate; a display panel spaced apart from the circuit substrate in a first direction; and a plurality of semiconductor packages between the circuit substrate and the display panel, and electrically connecting the circuit substrate and the display panel, wherein each of the semiconductor packages comprises: a film substrate; a connecting portion connected to the display panel; a first connection pad connected to the circuit substrate; a semiconductor chip on the film substrate; interconnection lines connected to the semiconductor chip; an interconnection protective layer on the interconnection lines; and a cutting pattern on the film substrate and spaced apart from the semiconductor chip, the display panel, and the circuit substrate, wherein the semiconductor chip comprises a first output pad connected to the connecting portion, and a second output pad connected to the first connection pad, wherein the interconnection lines comprise a first interconnection line connecting the connecting portion to the first output pad, and a second interconnection line connecting the first connection pad to the second output pad, and wherein the connecting portion, the first connection pad, the interconnection lines, and the cutting pattern comprise material”, as recited by independent claim 18, in combination with the other elements/steps of the claim. No prior art was found that taught this novel method/device.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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