DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/25/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 36-38, 40-43 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al (US Publication No. 2020/0286902) in view of Yamazaki et al (US Publication No. 2017/0077125) and in further view of Lee et al (US Patent No. 9773806).
Regarding claim 1, Fukuda discloses a semiconductor device, comprising: a stacked structure including conductive layers and insulating layers alternately stacked with each other Fig 3 ¶0073-0075; a channel layer Fig 3, 31 passing through the stacked structure Fig 3; a source layer Fig 3, SL; and a bit line Fig 1 ¶0090, wherein the channel layer is a single layer Fig 3, 31, the single layer including a first region Fig 3, 31, a second region, and a third region ¶0116-0119, and the first region (bottom portion) has a greater thickness than each of the second region and the third region, wherein the first region is adjacent to the source layer Fig 3, SL and is a channel region of a source select transistor Fig 3, and the third region is adjacent to the bit line Fig and Fig 3. Fukuda discloses all the limitations but silent on the thickness of the first region to be greater than the first and second region crossing the first direction. Whereas Yamazaki discloses first region has a greater thickness in a second direction crossing the first direction than each of the other region Fig 3B. Fukuda and Yamazaki are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Yamazaki since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Fukuda and Yamazaki discloses all the limitations but silent on the arrangement of the channels first region relative to the conductive layer. Whereas Lee discloses a first region is adjacent to the source layer, is a channel region of a source select transistor, and is overlapped with at least one of the conductive layers in the second direction Fig 4, Fig 5 and Fig 13. Fukuda and Lee are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Lee as an alternative arrangement to improve device performance.
Regarding claim 2, Fukuda discloses a gap-fill insulating layer Fig 3, 35 surrounded by the channel layer ¶0126-0128.
Regarding claim 3, Fukuda discloses wherein a first portion of the gap-fill insulating layer, corresponding to the first region, has a smaller width in the second direction than a second portion of the gap-fill insulating layer, corresponding to the second region Fig 30.
Regarding claim 4, Fukuda discloses wherein a first portion of the gap-fill insulating layer, corresponding to the first region, has a smaller diameter than a second portion of the gap-fill insulating layer, corresponding to the second region Fig 3.
Regarding claim 5, Fukuda discloses wherein the first portion of the gap-fill insulating layer has a smaller width than a third portion of the gap-fill insulating layer, corresponding to the third region Fig 2-3.
Regarding claim 6, Fukuda discloses wherein the first portion of the gap-fill insulating layer has a smaller diameter than a third portion of the gap-fill insulating layer, corresponding to the third region Fig 2-3.
Regarding claim 7, Fukuda discloses wherein the stacked structure is located between the source layer and the bit line Fig 1-3.
Regarding claim 8, Fukuda discloses wherein the second region is located between the first region and the third region Fig 1-3.
Regarding claim 9, Fukuda discloses a conductive pad configured to couple the channel layer to the bit line and configured to be in contact with the third region of the channel layer Fig 1 ¶0092-0095.
Regarding claim 36, Fukuda discloses a semiconductor device, comprising: a stacked structure including conductive layers and insulating layers alternately stacked with each other Fig 3 ¶0073-0075; a channel structure Fig 3 passing through the stacked structure, wherein the channel structure includes a channel layer Fig 3, 31, a memory layer, a gap-fill insulating layer; a source layer; and a bit line Fig 3 ¶0071, wherein the channel layer is a single layer Fig 3, 31, the single layer including a first region and a second region ¶0119, and the first region has a greater thickness than the second region Fig 3, wherein the first region is adjacent to the source layer and the second region is adjacent to the bit line Fig 1 and Fig 3. Fukuda discloses all the limitations but silent on the thickness of the first region to be greater than the first and second region crossing the first direction. Whereas Yamazaki discloses first region has a greater thickness in a second direction crossing the first direction than each of the other region Fig 3B. Fukuda and Yamazaki are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Yamazaki since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Fukuda and Yamazaki discloses all the limitations but silent on the arrangement of the channels first region relative to the conductive layer. Whereas Lee discloses a first region is overlapped with at least one of the conductive layers in the second direction Fig 4, Fig 5 and Fig 13. Fukuda and Lee are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Lee as an alternative arrangement to improve device performance.
Regarding claim 37, Fukuda discloses wherein the channel layer is coupled to the source layer Fig 1 and Fig 3.
Regarding claim 38, Fukuda discloses wherein the channel layer protrudes toward the source layer Fig 1 and Fig 3.
Regarding claim 40, Fukuda discloses wherein a first portion of the gap-fill insulating layer, corresponding to the first region, has a smaller width in the second direction than a second portion of the gap-fill insulating layer, corresponding to the second region Fig 1, Fig 3 and Fig 30.
Regarding claim 41, Fukuda discloses, wherein a first portion of the gap-fill insulating layer, corresponding to the first region, has a smaller diameter than a second portion of the gap-fill insulating layer, corresponding to the second region Fig 1 and Fig 3.
Regarding claim 42, Fukuda discloses wherein the stacked structure is located between the source layer and the bit line Fig 1 and Fig 3.
Regarding claim 43, Fukuda discloses wherein the memory layer surrounds a side of the channel layer Fig 1 and Fig 3.
Claims 10-16, 39 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al (US Publication No. 2020/0286902), Yamazaki et al (US Publication No. 2017/0077125) and Lee et al (US Patent No. 9773806) and in further view of Rabkin et al (US Publication No. 2020/0143888).
Regarding claim 10, Fukuda discloses all the limitations except silent on the erase operation. Whereas Rabkin discloses wherein the first region is a region where a current is generated during an erase operation ¶0028-0035. Fukuda and Rabkin are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Rabkin to improve device performance ¶0031-0035.
Regarding claim 11, Rabkin discloses wherein the first region and the second region are regions where a current is generated during an erase operation¶0028-0035.
Regarding claim 12, Fukuda discloses a semiconductor device, comprising: a source layer Fig 3, SL; and a bit line Fig 1 ¶0090; and a channel layer Fig 3, 31 coupled between the source layer Fig 3, SL and the bit line Fig 1, BL, wherein the channel layer is a single layer Fig 3, the single layer including a first region and a second region Fig 3, the first region is adjacent to the source layer Fig 3, the second region is adjacent to the bit line Fig 1 ¶0119, and the first region has a greater thickness than the second region Fig 3, and wherein the first region is a channel region of a source select transistor Fig 3. Fukuda discloses all the limitations except silent on the erase operation. Whereas Rabkin discloses wherein the first region is a region where a current is generated during an erase operation ¶0028-0035. Fukuda and Rabkin are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Rabkin to improve device performance ¶0031-0035. Fukuda and Rabkin disclose all the limitations but silent on the thickness of the first region to be greater than the first and second region crossing the first direction. Whereas Yamazaki discloses first region has a greater thickness in a second direction crossing the first direction than each of the other region Fig 3B. Fukuda and Yamazaki are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Yamazaki since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Fukuda, Yamazaki and Rabkin discloses all the limitations but silent on the arrangement of the channels first region relative to the conductive layer. Whereas Lee discloses a first region is overlapped with at least one of the conductive layers in the second direction Fig 4, Fig 5 and Fig 13. Fukuda and Lee are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Lee as an alternative arrangement to improve device performance.
Regarding claim 13, Fukuda discloses a gap-fill insulating layer surrounded by the channel layer ¶0126-0128.
Regarding claim 14, Fukuda discloses wherein a portion of the gap-fill insulating layer, corresponding to the first region, has a smaller width in the second direction than a portion of the gap-fill insulating layer, corresponding to the second region Fig 30.
Regarding claim 15, Fukuda discloses wherein a portion of the gap-fill insulating layer, corresponding to the first region, has a smaller diameter than a portion of the gap-fill insulating layer, corresponding to the second region Fig 3.
Regarding claim 16, Fukuda discloses a conductive pad configured to couple the channel layer to the bit line and configured to be in contact with the second region of the channel layer Fig 1 ¶0092-0095.
Regarding claim 39, Rabkin discloses wherein a portion of the channel layer protruding toward the source layer is surrounded by the source layer Fig 6A.
Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al (US Publication No. 2020/0286902), Yamazaki et al (US Publication No. 2017/0077125) and Lee et al (US Patent No. 9773806) and in further view of Kang et al (US Publication No. 2020/0328227).
Regarding claim 44, Fukuda discloses all the limitations but silent on the type of semiconductor layer. Whereas Kang discloses an epitaxial semiconductor between the channel layer and the source layer ¶0090 and 0103. Fukuda and Kang are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fukuda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fukuda and incorporate the teachings of Kang as an alternative material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Response to Arguments
Applicant’s arguments with respect to claims 1-16, 36-44 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811