Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 05/14/24. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 04/01/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the second line" in the body of the claim. There is insufficient antecedent basis for this limitation in the claim. This appears to be a typographical error and for purposes of examination, the above phrase is interpreted to mean “the second data line”. Appropriate correction is required.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-20 are rejected under 35 U.S.C. §102(a)(1) as being unpatentable over Sandhu (US 20130193400 A1).
Regarding claim 1, Sandhu discloses an apparatus comprising:
a conductive region (see figs 4 and 5 disclosing 40, 52); a first data line (see fig 5, disclosing left 18); a second data line(see fig 5, disclosing middle 18);
a first memory cell including a first transistor and a second transistor (see fig 2, 7 disclosing left and middle VFET), the first transistor (transistor under gate 36 right side)including a first channel region 22 coupled between the first data line 18 and the conductive region (40/52), and a first charge storage structure located between the first data line and the conductive region (see region 50 under 46), the second transistor (see fig 4, disclosing second transistor under gate 36 right side))including a second channel region 22 coupled to and located between the first data line 18 and the first charge structure 50;
a second memory cell (see fig 2, disclosing second memory cell, on right) including a third transistor and a fourth transistor (see right side memory cell where third and fourth transistors are under gates left and right 34), the third transistor including a third channel region 22 coupled between the second data line 18 and the conductive region 46, and a second charge storage 50 structure located between the second line and the conductive region (see 50 between 46 and 38), the fourth transistor including a fourth channel region 22 (see fig 2, where channel is under 34)coupled to and located between the second data line 18 and the second charge structure50;
a conductive structure located between the first and second charge storage structures (see portions of 46 is in between the segments to f50); and
a conductive line forming a gate of each of the first, second, third, and fourth transistors (see element 34 ).
Regarding claim 2, Sandhu discloses the apparatus of claim 1, wherein the conductive structure comprises one of metal and conductively doped polysilicon (see paras [0028] and [0029] disclosing conductive materials).
Regarding claim 3, Sandhu discloses he apparatus of claim 1, wherein the second channel region comprises a same material as the fourth channel region (see figs 2, 4, and 5 disclosing 22 being the same type but separate material).
Regarding claim 4, Sandhu discloses the apparatus of claim 1, wherein the first and third channel regions comprise a first material, and the second and fourth channel regions comprise a second material different from the first material(see figs 2, 4, and 5 disclosing 22 being the same type but separate material).
Regarding claim 5, Sandhu discloses the apparatus of claim 1, wherein the conductive structure contacts the conductive region (see elements 50/38 disclosing contact).
Regarding claim 6, Sandhu discloses the apparatus of claim 1, wherein the conductive structure is separated from the conductive region(see elements 50/38 disclosing contact and are separate elements 42, 40, 50, 46).
Regarding claim 7, Sandhu discloses the apparatus of claim 1, further comprising:
a third memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional channel region coupled between the first data line and the conductive region, and a first additional charge storage structure, the second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure (see fig 2, 4 and 5 disclosing at least four memory cells);
a fourth memory cell including a third additional transistor and a fourth additional transistor, the third additional transistor including a third additional channel region coupled between the second data line and the conductive region, and a second additional charge storage structure, the fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure(see fig 2, 4 and 5 disclosing at least four memory cells); and
wherein the conductive structure extends between the first additional charge storage structure and the second additional charge storage structure (see 46 extending between cells 14).
Regarding claim 9, Sandhu discloses the apparatus of claim 1, further comprising:
a third memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional channel region coupled between the first data line and the conductive region, and a first additional charge storage structure, the second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure(see fig 2, 4 and 5 disclosing at least four memory cells);
a fourth memory cell including a third additional transistor and a fourth additional transistor, the third additional transistor including a third additional channel region coupled between the second data line and the conductive region, and a second additional charge storage structure, the fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure(see fig 2, 4 and 5 disclosing at least four memory cells);
a first additional conductive structure located between the first and second additional charge storage structures (see element 46);
an additional conductive line forming a gate of each of the first, second, third, and fourth additional transistors, the conductive line and the additional conductive line located between the first memory cell and the first additional memory cell; and a second additional conductive structure extending in a direction from the first memory cell to the second memory cell, and the second additional conductive structure separated from the first and second charge storage structures and from the first and second additional charge storage structures (see element 46 being in between 14).
Regarding claim 10, Sandhu discloses the apparatus of claim 1, wherein the conductive region is a first conductive region, and the apparatus further comprising:
a second conductive region separated from the first conductive region (see 50 separated from 18/20);
a third memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional channel region coupled between the first data line and the second conductive region, and a first additional charge storage structure electrically, the second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure (see fig 2, 4 and 5 disclosing at least four memory cells);
a fourth memory cell including a third additional transistor and a fourth additional transistor, the third additional transistor including a third additional channel region coupled between the second data line and the second conductive region, and a second additional charge storage structure, the fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure (see fig 2, 4 and 5 disclosing at least four memory cells); and
wherein the conductive structure extends between the first additional charge storage structure and the second additional charge storage structure (see element 46).
Regarding claim 11, Sandhu discloses an apparatus comprising:
a conductive region located in a first level of the apparatus(see figs 2, 4-5 discloses 38, 40, 52, 46);
a first additional conductive region located in a second level of the apparatus (see figs 2, 4, 5, disclosing conductive region 16, 18, 20);
a second additional conductive region located in the second level (see fig 2, disclosing multiple 18/20);
a first memory cell 14 located between the first and second levels and including a first charge storage structure (see left 14, Fig 2), a first channel region 22 contacting the first charge storage structure 50 and the first additional conductive region (18/20), and a first semiconductor material contacting the first additional conductive region and the conductive region (see 22/26 contacting 18/20);
a second memory cell located between the first and second levels and including a second charge storage structure(see fig 2, 4, 5, ), a second channel region 22 contacting the second charge storage structure (see fig 2, 4, 5, where 22 is contacting 38) and the second additional conductive region (see 46, 50, 52), and a second semiconductor material contacting the second additional conductive region and the conductive region (see fig 2, 4, 5, disclosing 22 contacting 18/20 and 50);
a conductive structure located between first and second charge storage structures (see 46 formed across and between memory cells 14); and a conductive line spanning across part of each of the first semiconductor material (see fig 2, element 46), the first channel region, the second semiconductor material, and the second channel region(see fig 2, element 46).
Regarding claim 12, Sandhu discloses the apparatus of claim 11, wherein: the first additional conductive region is part of a first data line of the apparatus (see 46); and the second additional conductive region is part of a second data line of the apparatus (data line 46).
Regarding claim 13, Sandhu discloses the apparatus of claim 11, wherein the conductive line is part of an access line of the apparatus (see element 46).
Regarding claim 14, Sandhu discloses the apparatus of claim 11, wherein the conductive line further spans across part of each of the first and second charge storage structures (see element 46 spanning across multiple 14’s).
Regarding claim 15, Sandhu discloses the apparatus of claim 11, wherein the conductive structure contacts the conductive region (see 50/36).
Regarding claim 16, Sandhu discloses the apparatus of claim 11, wherein the conductive structure comprises metal (see paras [0029]-[0030]).
Regarding claim 17, Sandhu discloses an apparatus comprising:
a conductive region (see top region 52/50, 40);
a first additional conductive region separated from the conductive region (see 18/20 on the bottom);
a second additional conductive separated from the conductive region the first additional conductive region (see fig 5, disclosing multiple 20/18);
a first memory cell (see 14 fig 2, on right side)including a first charge storage structure (see 50), a first portion including an oxide material (see para [0022] 32), the first portion coupled between the first charge storage structure and the first additional conductive region (see 50), and a first semiconductor material coupled between the first additional conductive region and the conductive region 22 is between 50 and 18/20;
a second memory cell (14, see para right)located between the first and second levels and including a second charge storage structure (50), a second portion including an oxide material (see para [0022] disclosing 32 oxide), the second coupled between the second charge storage structure 50 and the second additional conductive region (fig 2, 20/18), and a second semiconductor material coupled between the second additional conductive region and the conductive region (22 between 20/18 and 50);
a conductive structure located between the first and second charge storage structures (see parts of 46 is between 14, fig 2); and
a conductive line spanning across part of each of the first semiconductor material, the first portion region, the second semiconductor material, and the second portion region(see parts of 46 is between 14, fig 2).
Regarding claim 18, Sandhu discloses the apparatus of claim 17, wherein the oxide material of each of the first portion and the first portion comprises a semiconducting oxide material (see para [0028] and [0029] disclosing oxide material).
Regarding claim 19, Sandhu disclose the apparatus of claim 17, wherein each of the first semiconductor material and the second semiconductor material includes a first type of material, and each of the first portion and the second portion includes a second type of material (see element 22 disclosing separate materials).
Regarding claim 20, Sandhu disclose the apparatus of claim 17, wherein the apparatus comprises a memory device, and the conductive line is part of a word line of the memory device (see word line, see para [0023], disclosing 36 is wordline).
Allowable Subject Matter
Claim 8 recites allowable subject matter. In particular, the cited art do not disclose an additional conductive structure extending in a direction perpendicular to the conductive structure, the additional conductive structure extending between the first and second charge storage structures and the first and second additional charge storage structures. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD CHIN/Primary Examiner, Art Unit 2893
Prosecution Insights