DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-6 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nandi (US 2017/0194943) in view of Yamashita (US 6,313,666).
Regarding claim 1, fig. 2 of Nandi discloses an edge-triggered flip-flop comprising: a first latch [104] including a first component [208] connected to an input data node [at 111] of the first latch; and a second latch [106] including a second transistor [222] having a gate connected to the first component without any intervening transistors, and an output data node [at 112] of the second latch connected to the second transistor. Nandi does not explicitly show where the first component/NAND gate 208 has a first transistor having a gate connected to an input data node of the first latch. However, fig. 4A of Yamashita discloses a transistor implementation of a NAND gate where the input is received at a gate of a transistor in the NAND gate and the output is output through another node of the transistor. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the NAND as taught in Yamashita for the purpose of utilizing a suitable and well-known type of NAND circuit implementation.
Regarding claim 2, the combination as indicated above discloses the input data node of the first latch driven from a circuit [102] outside of the first latch.
Regarding claim 3, the combination as indicated above discloses one and only one data input coupled to the input data node of the first latch; one and only one data output coupled to the output data node of the second latch; and one and only one clock input connected to one or more clock nodes of the first latch and one or more clock nodes of the second latch.
Regarding claim 4, the combination as indicated above discloses a first clocked feedback path [212, 214, 216] in the first latch; and a second clocked feedback path [e.g. 232] in the second latch.
Regarding claim 5, the combination as indicated above discloses a clock input node and an output data node of the first latch; and a clock input node and an input data node of the second latch; wherein the output data node of the first latch, the input data node of the second latch, the first transistor, and the gate of the second transistor are all connected.
Regarding claim 6, the combination as indicated above discloses wherein the clock input node of the first latch and the clock input node of the second latch are configured to receive clock signals having matching polarities (CLK 110 is used to control 214 in the first latch, and 224 and 232 of the second latch).
Regarding claim 8, the combination as indicated above discloses a first buffer [102] and a second buffer [120]; a single data input connected to an input of the first buffer with an output of the first buffer connected to the input data node of the first latch; and a single data output connected to an output of the second buffer with an input of the second buffer connected to the output data node of the second latch.
Regarding claim 9, the combination as indicated above discloses wherein both the first buffer and the second buffer are inverting buffers.
Regarding claim 10, the combination as indicated above discloses consisting of no more than 20 transistors, with the first latch and the second latch each respectively consisting of no more than 10 transistors (104 has 9 transistors and 106 has 7 transistors).
Allowable Subject Matter
Claims 7 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIBIN CHEN/Primary Examiner, Art Unit 2836
Prosecution Insights