DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-8, 12, and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 5-7 of U.S. Patent No. 11,967,955. Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claims are anticipated by the reference claims.
Election/Restrictions
Applicant’s election without traverse of the Subcombination and Species I of figures 1 and 4, claims 1-13 in the reply filed on 12/2/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2013/0049836).
Regarding claim 1, fig. 4 of Yang discloses an edge-triggered flip-flop comprising: a first latch [206] including a first transistor [PMOS with drain at M] having a gate connected to an input data node of the first latch; and a second latch [210] including a second transistor [PMOS with drain at S] having a gate connected to the first transistor and an output data node of the second latch connected to the second transistor.
Regarding claim 2, fig. 4 of Yang discloses the input data node of the first latch driven from a circuit outside of the first latch [e.g. 204].
Regarding claim 3, fig. 4 of Yang discloses one and only one data input [MN] coupled to the input data node of the first latch; one and only one data output [S] coupled to the output data node of the second latch; and one and only one clock input [e.g. CPN] connected to one or more clock nodes of the first latch and one or more clock nodes of the second latch.
Regarding claim 4, fig. 4 of Yang discloses a first clocked feedback path in the first latch [e.g. 216]; and a second clocked feedback path in the second latch [e.g. 212].
Regarding claim 5, fig. 4 of Yang discloses a clock input node and an output data node of the first latch; and a clock input node and an input data node of the second latch; wherein the output data node of the first latch, the input data node of the second latch, the first transistor, and the gate of the second transistor are all connected.
Regarding claim 6, fig. 4 of Yang discloses wherein the clock input node of the first latch and the clock input node of the second latch are configured to receive clock signals having matching polarities.
Regarding claim 7, fig. 4 of Yang discloses the first latch and the second latch both respectively further comprising: two serially connected p-channel transistors [top PMOS in 206 and 210 that feedback to control the respective output data node] to couple their respective output data node to a VDD supply line; and two serially connected n-channel transistors [bottom NMOS in 206 and 210 that feedback to control the respective output data node] to couple their respective output data node to a Vss supply line.
Regarding claim 8, fig. 4 of Yang discloses a first buffer [204] and a second buffer [406]; a single data input connected to an input of the first buffer with an output of the first buffer connected to the input data node of the first latch; and a single data output connected to an output of the second buffer with an input of the second buffer connected to the output data node of the second latch.
Regarding claim 9, fig. 4 of Yang discloses wherein both the first buffer and the second buffer are inverting buffers.
Regarding claim 10, fig. 4 of Yang discloses consisting of no more than 20 transistors, with the first latch and the second latch each respectively consisting of no more than 10 transistors.
Claim(s) 1-6, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato (US 6,369,629).
Regarding claim 1, fig. 2 of Sato discloses an edge-triggered flip-flop comprising: a first latch [on the left of fig. 2] including a first transistor [12] having a gate connected to an input data node of the first latch; and a second latch [on the right of fig. 2] including a second transistor [16] having a gate connected to the first transistor (through NAND 10) and an output data node of the second latch connected to the second transistor.
Regarding claim 2, fig. 2 of Sato discloses the input data node of the first latch driven from a circuit outside of the first latch.
Regarding claim 3, fig. 2 of Sato discloses one and only one data input [D] coupled to the input data node of the first latch; one and only one data output [Q] coupled to the output data node of the second latch; and one and only one clock input [CK] connected to one or more clock nodes of the first latch and one or more clock nodes of the second latch.
Regarding claim 4, fig. 2 of Sato discloses a first clocked feedback path in the first latch [21-23]; and a second clocked feedback path in the second latch [20, 26, 27].
Regarding claim 5, fig. 2 of Sato discloses a clock input node and an output data node of the first latch; and a clock input node and an input data node of the second latch; wherein the output data node of the first latch, the input data node of the second latch, the first transistor, and the gate of the second transistor are all connected.
Regarding claim 6, fig. 2 of Sato discloses wherein the clock input node of the first latch and the clock input node of the second latch are configured to receive clock signals having matching polarities.
Regarding claim 10, fig. 2 of Sato discloses consisting of no more than 20 transistors, with the first latch and the second latch each respectively consisting of no more than 10 transistors (col. 8, lines 25-27).
Regarding claim 11, fig. 2 of Sato discloses consisting of no more than 19 transistors (col. 8, lines 25-27), wherein a clocked pull-up current path in the first latch and clocked pull-up current path in the second latch share a p-channel transistor having a gate connected to a clock input of the edge- triggered flip-flop (col. 8, lines 20-23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Sato.
Regarding claim 11, Yang discloses the device as indicated above. Yang further discloses where the flip-flop consists of no more than 19 transistors. Yang does not disclose wherein a clocked pull-up current path in the first latch and clocked pull-up current path in the second latch share a p-channel transistor having a gate connected to a clock input of the edge- triggered flip-flop. However, fig. 2 of Sato describes where a master and a slave latch share a clocked pull-up transistor 11 (col. 8, lines 20-23). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the shared pull-up transistor as taught in Sato for the purpose of utilizing a suitable and well-known type of flip-flop design to save space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang describes a master and slave latch. Rao describes a fault resilient flip-flop with balanced topology.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIBIN CHEN/Primary Examiner, Art Unit 2896