CTNF 18/624,084 CTNF 82751 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 3/13/2026 and 4/02/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Priority 02-27 AIA Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 2023-077022 , filed on May 10, 2023 . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-6 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Senoo (US Publication No. 2016/0351561) . Regarding claim 1, Senoo discloses a semiconductor device, comprising a chip of a reverse conducting IGBT (RC-IGBT) including: an IGBT region (14a) functioning as an insulated gate bipolar transistor (IGBT) a plurality of diode regions (14b) functioning as a diode wherein the plurality of diode regions (14b) are disposed to form an island-like shape in an effective region which is a region made up of the IGBT region (14a) and the diode regions (Figure 4) when a length of one side of one of the diode regions is WD, an interval of the diode regions adjacent to each other is WI, a length of one side of the effective region is WC, and a thickness of the chip is t (80um-165um), satisfied are relationships of (paragraph 28): 2t (240um) < WD < 5t (600um) 2t (240um) < WI < 5t (600um) WD + WI < WC/6 (paragraph 29) Regarding claim 2, Senoo discloses both the length (WD) of one side of one of the diode regions and the interval (WI) of the diode regions adjacent to each other are equal to or larger than 160 μm and equal to or smaller than 400μm (paragraph 29 shows 300um). Regarding claim 3, Senoo discloses a gate wiring region where a gate wiring connecting a gate electrode (34) of the IGBT and a gate pad (12) is disposed is not provided in the effective region, but is provided to an outer surrounding part of the effective region (paragraph 43). Regarding claim 4, Senoo discloses each of the diode regions includes a trench gate (30) extending to a first direction and an intersection trench gate (30) extending to a second direction perpendicular to the first direction as an active trench gate in which a gate electrode (34) of the IGBT (14a) is embedded, and the intersection trench gate is connected to a gate wiring connecting the gate electrode (34) of the IGBT and a gate pad (12) in the outer surrounding part of the effective region (paragraphs 35-36 and 43; Figure 2). Regarding claim 5, Senoo discloses the intersection trench gate (30) extends along an end portion of each of the diode regions (14b) (Figure 3). Regarding claim 6, Senoo discloses each of the diode regions (14b) and the IGBT region (14a) have a same structure on a side of a first main surface, and have structures different from each other on a side of a second main surface (Figure 5) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Senoo (US Publication No. 2016/0351561) in view of Hikasa (US Publication No. 2023/0343868) . Regarding claim 7, Senoo discloses the limitations as discussed in the rejection of claim 1 above. Senoo does not disclose the chip further includes a temperature sensing diode disposed on an outer side of the effective region in a plan view. However, Hikasa discloses including a temperature sensor (290) at an outer side of the effective region in a plan view (Figures 21-22). It would have been obvious to one of ordinary skill in the art a time before the effective filing date of the invention to have modified the device of Senoo to include a temperature sensor at the outer side of the effective region, as taught by Hikasa, since it can provide temperature sensing to protect the device from overheating without a reduction in area of the active region (paragraph 313). Regarding claim 8, Hikasa discloses the chip further includes a laminated metal layer including a metal layer disposed on an upper side of the effective region and a plating layer on the metal layer (paragraphs 158-161). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Senoo in view of Hikasa . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoshi (US Publication No. 2020/0373292) discloses a length/width relationship of connecting regions (paragraphs 111-113) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 6/9/2026 Examiner, Art Unit 2897 /JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/624,084 Page 2 Art Unit: 2897 Application/Control Number: 18/624,084 Page 3 Art Unit: 2897 Application/Control Number: 18/624,084 Page 4 Art Unit: 2897 Application/Control Number: 18/624,084 Page 5 Art Unit: 2897
Prosecution Insights