DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 7/6/2026 "Reply" elects without traverse and identifies claims 1-10 as being drawn to Species A. Accordingly, Examiner has withdrawn claims 11-20 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 5/5/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marimuthu (US Pub. No. 2010/0133704).
Regarding claim 1, in FIG. 9g, Marimuthu discloses a semiconductor package, comprising: a lower redistribution wiring layer (522) having lower redistribution wirings; at least one semiconductor chip (502) disposed on, and electrically connected to, the lower redistribution wiring layer; a sealing member (518/504/506) disposed on the lower redistribution wiring layer, the sealing member having a plurality of through vias (514) that penetrate the sealing member and are electrically connected to the lower redistribution wirings; a dummy substrate layer (554/534/540/542, capable of being used in this manner) stacked on the sealing member and the at least one semiconductor chip, the dummy substrate layer having a plurality of through electrodes (544) that penetrate the dummy substrate layer and are electrically connected to the plurality of through vias; and an upper redistribution wiring layer (556) disposed on the dummy substrate layer, the upper redistribution wiring layer having upper redistribution wirings (558/562) that are electrically connected to the plurality of through electrodes.
Regarding claim 2, in FIG. 9g, Marimuthu discloses a first dielectric layer (portion of 518 containing bond pad beneath 552) provided on an upper surface of the sealing member and having a plurality of first bonding pads (bond pad beneath 552) that are connected to end portions of the plurality of through vias respectively; and a second dielectric layer (portion of 554 containing 550) forming a lower surface of the dummy substrate layer and having a plurality of second bonding pads (550) that are connected to at least some of the plurality of through electrodes respectively.
Regarding claim 3, in FIG. 9g, Marimuthu discloses that the plurality of first bonding pads are in contact (at least electrically) with the plurality of second bonding pads respectively, and the first dielectric layer is in contact with the second dielectric layer.
Regarding claim 7, in FIG. 9g, Marimuthu discloses that the dummy substrate layer includes a silicon material (540/542, vias are through silicon vias, paragraph [0083]).
Regarding claim 8, in FIG. 9g, Marimuthu discloses that the plurality of through electrodes comprise a plurality of dummy through electrodes (capable of being used in this manner) that are provided to penetrate the dummy substrate layer on the at least one semiconductor chip.
Regarding claim 9, in FIG. 9g, Marimuthu discloses that the sealing member surrounds the at least one semiconductor chip.
Regarding claim 10, in FIG. 9g, Marimuthu discloses a second package (560) disposed on the upper redistribution wiring layer, wherein the second package includes a package substrate (564) and at least one second semiconductor chip (paragraph [0085]) stacked on the package substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu (US Pub. No. 2010/0133704) in view of Chiou (US Pub. No. 2011/0065238).
Regarding claim 4, Marimuthu appears not to explicitly disclose that the first dielectric layer and second dielectric layer (portion of molding compounds 518/554) include silicon oxide, silicon nitride or silicon oxynitride.
The art however well recognized silicon oxide to be suitable for use as a molding compound. See, for example, Chiou, paragraph [0015].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Thornton disclosed first dielectric layer and second dielectric layer from silicon oxide for its recognized suitability as a molding compound.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu (US Pub. No. 2010/0133704).
Regarding claim 5, Marimuthu appears not to explicitly disclose that a thickness of the dummy substrate layer is within a range of about 30 μm to 500 μm. There is no evidence showing the criticality of the claimed thickness.
The semiconductor art well recognized that substrate thickness controls parameters critical for device performance, including overall device thickness and mechanical viability (e.g. warping, strength, etc.). Substrate thickness is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to determine (for example by routine experimentation) the optimum dummy substrate thickness.
Regarding claim 6, Marimuthu appears not to explicitly disclose that a diameter of each of the plurality of through vias is within a range of about 30 μm to 300 μm, and a diameter of each of the plurality of through electrodes is within a range of about 5 μm to 50 μm. There is no evidence showing the criticality of the claimed thicknesses.
The semiconductor art well recognized that conductor thickness (or diameter) controls parameters critical for device performance, including resistance (resistivity, length and cross sectional area) and mechanical viability (which includes strength as imparted by conductor thickness). Conductor thickness is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to determine (for example by routine experimentation) the optimum through via/electrode diameter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
Prosecution Insights