DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 3, 2024.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of Manufacturing Strained Vertical Channel FET.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu (CN112582464A), hereinafter Zhu169.
It is noted that the Examiner is using (US20220190169A1) as a convenient English translation.
Claim 1, Zhu169 discloses a method of manufacturing a semiconductor device, comprising:
forming a channel defining layer (channel layer formed on the sidewall of the second material layer, hereinafter, channel defining layer 1003, [0029], Fig. 10(a)) and a source/drain layer (third material layer may define a position of an upper end of the source/drain portions, hereinafter, source/drain layer 1005, [0029], Fig. 10(a)) sequentially on a substrate (substrate 1001 includes the first material layer, hereinafter, substrate 1001, [0029], Fig. 10(a)) of a crystalline material (channel-defining layer 1003 and source/drain layer 1005 include a single crystal semiconductor material, [0023], Fig. 10(a));
patterning the channel defining layer 1003 and the source/drain layer 1005 as a ridge protruding relative to the substrate 1001 (channel defining layer 1003 and the source/drain layer 1005 are patterned into a ridge protruding relative to the substrate 1001, [0037], Fig. 4);
forming a channel layer (first active layer 1025 is a channel layer, hereinafter, channel layer 1025, [0068], Fig. 10(a)) on a sidewall of the ridge by deposition (channel layer 1025 is formed on a sidewall of the ridge by deposition, [0068], Fig. 10(a)); and
performing a crystallization process to recrystallize the channel layer 1025 (thermal annealing is a crystallization process that is performed to recrystallize the channel layer 1025, [0048]).
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Figure 4 from Zhu169
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Figure 10(a) from Zhu169
Claim 2, Zhu169 discloses the method according to claim 1, wherein an etching is performed into the substrate 1001 when patterning the ridge (an etching is performed on the channel defining layer 1003 and the source/drain layer 1005, which are patterned into a ridge into the substrate 1001, [0064], Fig. 4), so that the substrate 1001 has a protruding part corresponding to the source/drain layer 1005 (substrate 1001 has a protruding part corresponding to the source/drain layer 1005 , [0064], Fig. 10(a)), and
wherein before forming the channel layer 1025, the method further comprises:
selective etching the channel defining layer 1003 (a selective etching is performed on the channel defining layer 1003, [0064], Fig. 4), so that a sidewall of the channel defining layer 1003 is laterally recessed (a selective etching is performed on the channel defining layer 1003 so that a sidewall of the channel defining layer 1003 is laterally recessed, [0066], Fig. 8) relative to a sidewall of the source/drain layer 1005 and a sidewall of the protruding part of the substrate 1001 (a selective etching is performed on the channel defining layer 1003 so that a sidewall of the channel defining layer 1003 is laterally recessed relative to a sidewall of the source/drain layer 1005 and a sidewall of the protruding part of the substrate 1001, [0066], Fig. 8).
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Figure 8 from Zhu169
Claim 8, Zhu169 discloses the method according to claim 1, further comprising:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, hereinafter dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)); and
forming a cap layer on the dielectric layer 1031’ to adjust a stress (second position holding layer 1027, hereinafter cap layer 1027, used to adjust stress and is formed on top of dielectric layer 1031’, [0089], Fig. 14(b)).
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Figure 14(b) from Zhu169
Claim 19, Zhu169 discloses the method according to claim 2, further comprising:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)); and
forming a cap layer on the dielectric layer 1031’ to adjust a stress (second position holding layer 1027, hereinafter cap layer 1027, used to adjust stress and is formed on top of dielectric layer 1031’, [0089], Fig. 14(b)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 6, 7, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of Zhu (US20210175355A1), hereinafter Zhu355.
Claim 3, Zhu169 discloses the method according to claim 2, wherein after forming the channel layer 1025, the method further comprises:
removing the channel defining layer 1003 through selective etching (a selective etching is performed on the channel defining layer 1003, [0075], Fig. 10(b)).
Zhu169 does not explicitly disclose wherein after forming the channel layer 1025, the method further comprises:
etching a central part of the ridge while retaining a peripheral part of the ridge, so that the source/drain layer 1005, the channel defining layer 1003, and the protruding part of the substrate 1001 are in an annular shape.
However, Zhu355 discloses an annular-shaped stack comprising a source/drain layer 1005, a channel defining layer 1003, and a protruding part of the substrate 1001 (third material layer 1005, second material layer 1003, and the upper portion of the substrate 1001 selectively etched so that a peripheral part of the ridge is retained, [0007], [0053] and Fig 10).
Having an annular-shaped stack would improve heat dissipation efficiency and therefore reduce mechanical stress in the stack.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 by etching the source/drain layer 1005, the channel defining layer 1003, and the protruding part of the substrate 1001 are in an annular shape in order to manufacture a more thermally-efficient and robust device.
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Figure 10(b) from Zhu169
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Figure 10 from Zhu355
Claim 6, the combination of Zhu169 and Zhu355 teaches the method according to claim 3.
Zhu169 further discloses wherein patterning the ridge comprises:
forming a mandrel layer on the source/drain layer 1005 (layer 1011 used for a mandrel, hereinafter, mandrel layer 1011, formed on the source/drain layer 1005, [0052], Fig. 2) and forming a hard mask layer on the mandrel layer 1011 (hard mask layer 1013, hereinafter, hard mask layer 1013, may be formed on the mandrel layer 1011, [0053], Fig. 2);
patterning the hard mask layer 1013 (Figures 2 and 3 show the hard mask layer 1013 before and after being patterned respectively), and the mandrel layer 1011 (mandrel layer 1011 may be patterned, [0054], Figures 2 and 3 show the mandrel layer 1011, before and after being patterned respectively);
forming a spacer (spacer 1017, hereinafter, spacer 1017, [0056], Fig. 4) on a peripheral sidewall of the mandrel layer 1011 and a peripheral sidewall of the hard mask layer 1013 (a spacer 1017, is formed on a peripheral sidewall of the mandrel layer 1011 and a peripheral sidewall of the hard mask layer 1013, Fig. 4); and
selectively etching, by using the hard mask layer 1013 and the spacer 1017 as an etching mask, the source/drain layer 1005 and the channel defining layer 1003 sequentially, and selectively etching a part of the substrate 1001 (the hard mask layer 1013 and the spacer 1017 are used as an etching mask to selectively etch the source/drain layer 1005 and the channel defining layer 1003 sequentially, [0064], Fig. 7), and wherein etching the central part of the ridge comprises:
forming a dielectric layer on the substrate 1001 to cover a region outside the ridge (the dielectric layer 1031’, hereinafter dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b));
performing a planarization process on the dielectric layer 1031’ (the dielectric layer 1031’ is planarized, [0086], Fig. 14(b)), the spacer 1017, and the hard mask layer 1013 to expose the mandrel layer 1011 (performing a planarization process on the spacer 1017, and the hard mask layer 1013 to expose the mandrel layer 1011, [0096]); and
removing the mandrel layer 1011 by selective etching (mandrel layer 1011 may be removed by selective etching, [0096], Fig. 16), and further etching downwards into the substrate 1001 to expose the channel defining layer 1003 (the channel defining layer 1003 and the substrate 1001 may be selectively etched, [0097], Fig. 16).
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Figure 2 from Zhu169
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Figure 3 from Zhu169
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Figure 7 from Zhu169
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Figure 16 from Zhu169
Claim 7, the combination of Zhu169 and Zhu355 teaches the method according to claim 3.
Zhu169 further discloses the method according to claim 3 wherein the method according to claim 3 further comprises:
forming a gate stack, wherein the gate stack comprises a part between a top surface of the substrate 1001 and a bottom surface of the source/drain layer 1005, so as to surround the channel layer 1025 on inner and outer sides of the channel layer 1025 (the gate stacks 1037/1039 and 1037’/1039’ are formed on the outer and inner sides of the channel defining layer 1025, [0118]).
Claim 16, Zhu169 discloses the method according to claim 1, wherein the source/drain layer 1005 comprises a semiconductor material (the source/drain layer 1005 comprises a semiconductor material, [0050]), the channel defining layer 1003 and the source/drain layer 1005 are formed by deposition (the channel defining layer 1003 and the source/drain layer 1005 are formed by deposition, [0049]); or
the channel defining layer 1003 comprises a semiconductor material, and the source/drain layer 1005 comprises a semiconductor material (the channel defining layer 1003 comprises a semiconductor material, and the source/drain layer 1005 comprises a semiconductor material [0050]), the channel defining layer 1003 and the source/drain layer 1005 are formed by epitaxial growth (the channel defining layer 1003 and the source/drain layer 1005 are formed by epitaxial growth, [0049]), and
wherein the channel defining layer 1003 has an etching selectivity relative to the substrate 1001 and the source/drain layer 1005 (etching selectivity of the channel defining layer 1003 relative to the substrate 1001 and the source/drain layer 1005, [0061]).
Zhu169 does not explicitly disclose wherein the channel defining layer 1003 comprises a dielectric material.
However, Zhu355 teaches a channel defining layer (second material layer 1003, [0031], Fig. 10) and a source/drain layer (third material layer 1005, [0031], Fig. 10) being formed by deposition sequentially on a substrate (On the substrate 1001, a second material layer 1003 and a third material layer 1005 may be formed by epitaxial growth, [0031]), wherein the channel defining layer may comprise a dielectric material to form a dummy gate to facilitate subsequent processing of the source/drain portion (second material layer 1003 may be replaced with a dielectric material to form a dummy gate to facilitate subsequent processing of the source/drain portion, [0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the channel defining layer 1003 of the invention disclosed by Zhu169 with a dielectric material to form a dummy gate to facilitate subsequent processing of the source/drain portion as suggested by Zhu355.
Claim 20, the combination of Zhu169 and Zhu355 teaches the method according to claim 3.
Zhu169 further discloses the method according to claim 3 wherein the method according to claim 3 further comprises:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)); and
forming a cap layer on the dielectric layer to adjust a stress (second position holding layer 1027, used to adjust stress and is formed on top of dielectric layer 1031’, [0089], Fig. 14(b)).
Claims 4, 9, 10, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of REBOH (US20220293414A1).
Claim 4, Zhu169 discloses the method according to claim 1, further comprising:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, hereinafter dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)).
Zhu169 does not explicitly disclose fabricating samples with dielectric layers of different thicknesses, and testing an effect of the thickness of the dielectric layer 1031’ on the crystallization process.
However, REBOH teaches a dielectric layer, with a varying thickness (strain donor layer 108 comprising SiN, [0091], and having a thickness between 10nm and 1μm, [0095]), having an effect on the crystallization process of a semiconductor layer (modification of strain state in the semiconductor layer 104 before a heat treatment is carried out, [0099]).
The thickness of the dielectric layer is a result effective variable as one would have chosen the thickness of the dielectric layer to change the transmittance of light from UV lasers used for annealing of semiconductor materials to allow operating a modification of the strain state of the semiconductor layer and achieve a higher heating efficiency as suggested by REBOH in [0092].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 with the claimed range disclosed by REBOH as it would merely result in an optimization of a result effective variable.
Claim 9, Zhu169 discloses the method according to claim 8, wherein the cap layer 1027 comprises a compressive stress film and/or a tensile stress film (Zhu 169 discloses cap layer 1027 is a compressive stress film and/or a tensile stress film [0093]).
Zhu169 does not explicitly disclose the cap layer 1027 achieving a stress on the channel layer 1025 is in a range of -5GPa to 5GPa before the crystallization process.
However, REBOH teaches a strain donor layer 108 comprising an intrinsic strain between -8GPa and 8GPa imparting a strain on semiconductor layer 104 [0089], further comprising the channel region of one or more transistors [0122].
The stress on the channel layer 1025 is a result effective variable as one would have chosen the stress on the channel layer 1025 to maximize the carrier mobility and avoid applying strain-induced defects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 with the claimed range disclosed by REBOH as it would merely result in an optimization of a result effective variable.
Claim 10, the combination of Zhu169 and REBOH teaches the method according to claim 9.
REBOH further teaches wherein the intrinsic strain of the strain donor layer 108 is 1.5GPa (comprising an intrinsic strain between -8GPa and 8GPa imparting a strain on semiconductor layer 104 [0089]).
Claim 14, Zhu169 discloses the method according to claim 1.
Zhu169 does not explicitly disclose wherein the crystallization process comprises a laser annealing with an intensity in a range of about 1J/cm2 to 2J/cm2.
However, REBOH teaches a laser annealing with an intensity between 0.01J/cm2 to 2J/cm2 in [0114].
The intensity is a result effective variable as one would have chosen the intensity to increase the activation levels of B and P dopants and limit diffusion during the laser annealing process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 with the claimed range disclosed by REBOH as it would merely result in an optimization of a result effective variable.
Claim 17, Zhu169 discloses the method according to claim 2, further comprising:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)).
Zhu169 does not explicitly disclose fabricating samples with dielectric layers of different thicknesses, and testing an effect of the thickness of the dielectric layer 1031’ on the crystallization process.
However, REBOH teaches a dielectric layer, with a varying thickness (strain donor layer 108 comprising SiN, [0091], and having a thickness between 10nm and 1μm, [0095]), having an effect on the crystallization process of a semiconductor layer (modification of strain state in the semiconductor layer 104 before a heat treatment is carried out, [0099]).
The thickness of the dielectric layer is a result effective variable as one would have chosen the thickness of the dielectric layer to change the transmittance of light from UV lasers used for annealing of semiconductor materials to allow operating a modification of the strain state of the semiconductor layer and achieve a higher heating efficiency as suggested by REBOH in [0092].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 with the claimed range disclosed by REBOH as it would merely result in an optimization of a result effective variable.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of Zhu355 further in view of YOSHIMORI (US20120007151A1).
Claim 5, the combination of Zhu169 and Zhu355 teaches the method according to claim 3.
The combination of Zhu169 and Zhu355 does not explicitly teach wherein after performing the crystallization process, the method further comprises:
performing a tilted ion implantation with a first energy, so as to form a first doping region; and
performing a vertical ion implantation with a second energy higher than the first energy, so as to form a second doping region below the first doping region.
However, YOSHIMORI teaches performing a tilted ion implantation with a first energy, so as to form a first doping region (doping region 5n formed by tilted ion implantation with a first energy, [0116], Fig. 7); and
performing a vertical ion implantation with a second energy higher than the first energy, so as to form a second doping region below the first doping region (doping region 11, below doping region 5n, formed by vertical ion implantation with an energy higher than the first energy, [0113], Fig. 7).
As suggested by Zhu169 in [0068], the channel layer 1025 may be doped to adjust a threshold voltage of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of Zhu169 and Zhu355 by performing the ion implantation process taught by YOSHIMORI after the crystallization process in order to adjust the threshold voltage of the device.
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Figure 7 from YOSHIMORI
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of Wang (US20220359752A1).
Claim 11, Zhu169 discloses the method according to claim 8, wherein the dielectric layer 1031’ comprises an oxide (the dielectric layer 1031’ may comprise an oxide, [0086]).
Zhu does not explicitly disclose the cap layer 1027 comprising an oxide lining layer and a nitride layer.
However, Wang teaches a cap layer comprising an oxide lining layer and a nitride layer (dielectric layer 312 disposed on stress film 302 may be a cap layer, Fig. 9B, wherein the stress film 302 may include an oxide lining layer or a nitride layer, [0031], and dielectric layer 312 may include an oxide lining layer or a nitride layer).
Cap layers comprising oxide and nitride layers help relieve stress between the substrate and subsequent layers, reduce stress-induced dislocations, and protect sensitive device components during chemical and crystallization processes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Zhu169 by using a cap layer comprising an oxide lining layer and a nitride layer to protect the channel layer 1025 from stress-induced dislocations and help relieve stress between the channel layer and the surrounding structures including the protruding part of the substrate 1001, the channel defining layer 1003, and the source/drain layer 1005.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of REBOH further in view of YAMAZAKI (US20180114855A1).
Claim 12, the combination of Zhu169 and REBOH teaches the method according to claim 4.
The combination of Zhu169 and REBOH does not explicitly disclose wherein a thickness of the dielectric layer 1031’ is in a range of about 280 nm to 420 nm.
However, YAMAZAKI teaches a thickness of a dielectric layer being greater than or equal to 30nm and less than or equal to 500nm (insulating film 118, [0209]).
The thickness of the dielectric layer is a result effective variable as one would have chosen the thickness of the dielectric layer to apply the amount of stress to the channel layer 1025 that maximizes the carrier mobility and avoids applying strain-induced defects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention taught by the combination of Zhu169 and REBOH with the claimed range disclosed by YAMAZAKI as it would merely result in an optimization of a result effective variable.
Claim 13, the combination of Zhu169, REBOH, and YAMAZAKI teaches the method according to claim 12.
YAMAZAKI further teaches a thickness of a dielectric layer being 420nm (insulating film 118 having a thickness being greater than or equal to 30nm and less than or equal to 500nm, [0209]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of REBOH further in view of Duffy (US20150364561A1).
Claim 15, the combination of Zhu169 and REBOH teaches the method according to claim 14.
The combination of Zhu169 and REBOH does not explicitly teach wherein in the laser annealing, a laser depth is near a top surface of the substrate 1001 adjoining the channel layer 1025.
However, Duffy discloses a laser depth (penetration depth of a laser pulse, [0024]) near a top surface of a substrate adjoining a channel layer (NiGe channel layer on top of a Ge substrate, [0024]).
As taught by Duffy in [0024], “… the energy density of the laser anneal process can tailor the melt depth at the Ge surface, and thus control the thickness of the nickel-germanide layer that is formed.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by Zhu169 and REBOH by setting the laser depth to achieve the desired thickness of the channel layer.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu169 in view of Zhu355, and further in view of REBOH.
Claim 18, the combination of Zhu169 and Zhu355 teaches the method according to claim 3.
Zhu169 further discloses the method according to claim 3 wherein the method according to claim 3 further comprises:
forming a dielectric layer on the substrate 1001 to cover the substrate 1001, the ridge, and the channel layer 1025 (the dielectric layer 1031’, is formed to cover the substrate 1001, the ridge, and the channel layer 1025, [0086], Fig. 14(b)).
Neither Zhu169 nor Zhu355 explicitly disclose fabricating samples with dielectric layers of different thicknesses, and testing an effect of the thickness of the dielectric layer 1031’ on the crystallization process.
However, REBOH teaches a dielectric layer, with a varying thickness (strain donor layer 108 comprising SiN, [0091], and having a thickness between 10nm and 1μm, [0095]), having an effect on the crystallization process of a semiconductor layer (modification of strain state in the semiconductor layer 104 before a heat treatment is carried out, [0099]).
The thickness of the dielectric layer is a result effective variable as one would have chosen the thickness of the dielectric layer to change the transmittance of light from UV lasers used for annealing of semiconductor materials to allow operating a modification of the strain state of the semiconductor layer and achieve a higher heating efficiency as suggested by REBOH in [0092].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Zhu169 with the claimed range disclosed by REBOH as it would merely result in an optimization of a result effective variable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KURIBAYASHI (US20170047408A1)- KURIBAYASHI teaches a furnace annealing at a temperature in a range of about 600 ˚C to 900 ˚C for about 1 hour to 10 hours (execution of thermal treatment for a semiconductor wafer … at a temperature equal to or lower than about 1500 ˚C and for a time period equal to or longer than about one hour and equal to or shorter than about 10 hours, [0062]).
CHENG (US20110291100A1)- CHENG discloses an annealing step to recrystallize a semiconductor layer (recrystallized layer 18, [0031]) including a temperature between about 900 ˚C to 1100 ˚C for about 0 seconds to 5 seconds ([0034]).
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/MICHAEL M VANYO/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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