DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on September 3, 2026, have been accepted and entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a first molding material layer formed a space between the first memory die and the first interconnect die" in lines 13-14 on page 5. It is unclear if the act of forming the “first molding material layer” caused a space to be formed “between the first memory die and the first interconnect die” or the “first molding material layer” was formed in a space “between the first memory die and the first interconnect die” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of examination, the Examiner will interpret “a first molding material layer formed a space between the first memory die and the first interconnect die” as “a first molding material layer formed in a space between the first memory die and the first interconnect die”
Claim 1 recites the limitation "a second molding material layer formed a space between the second memory die and the first interconnect die" in lines 15-16 on page 5. It is unclear if the act of forming the “second molding material layer” caused a space to be formed “between the second memory die and the first interconnect die” or the “second molding material layer” was formed in a space “between the second memory die and the first interconnect die” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of examination, the Examiner will interpret “a second molding material layer formed a space between the second memory die and the first interconnect die” as “a second molding material layer formed in a space between the second memory die and the first interconnect die”
Claim 7 recites the limitation "a third molding material layer formed a space between the third memory die and the second interconnect die" in lines 6-7 on page 7. It is unclear if the act of forming the “third molding material layer” caused a space to be formed “between the third memory die and the second interconnect die” or the “third molding material layer” was formed in a space “between the third memory die and the second interconnect die” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of examination, the Examiner will interpret “a third molding material layer formed a space between the third memory die and the second interconnect die” as “a third molding material layer formed in a space between the third memory die and the second interconnect die”
Claim 7 recites the limitation "a fourth molding material layer formed a space between the third memory die and the second interconnect die" in lines 8-9 on page 7. It is unclear if the act of forming the “fourth molding material layer” caused a space to be formed “between the fourth memory die and the second interconnect die” or the “fourth molding material layer” was formed in a space “between the fourth memory die and the second interconnect die” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of examination, the Examiner will interpret “a fourth molding material layer formed a space between the third memory die and the second interconnect die” as “a fourth molding material layer formed in a space between the third memory die and the second interconnect die”
Claim 7 recites the limitation "the second substrate layer" in lines 10-11 on page 7. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret this instance of “the second substrate layer” as “a second substrate layer.”
Claim 11 recites the limitation "a second substrate layer" in line 25 on page 7. This limitation has already been introduced in claim 7 which claim 11 is dependent on and there is no surrounding claim language indicating that this is a different “second substrate layer” from the one already introduced.
For purposes of examination, the Examiner will interpret this instance of “a second substrate layer” as “the second substrate layer.”
The balance of claims are rejected for being dependent upon an already rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 11, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai. Et al. (US 20210305226 A1) in view of Yu. Et al. (US 20210118858 A1).
Claim 1, Tsai discloses a semiconductor structure (semiconductor structure S5 in [0083] and Annotated Fig. 2D, hereinafter, semiconductor structure S5), comprising;
a logic wafer (logic wafer 112 in [0012] and Annotated Fig. 2D, hereinafter, logic wafer 112);
a first front-side redistribution layer (RDL), (redistribution layer RDL1d in [0089] and Annotated Fig. 2D, hereinafter, first front-side RDL1d) disposed over logic wafer 112 (the first front-side RDL1d disposed between the logic wafer 112 and the die stack structure 150' in [0089] and Annotated Fig. 2D);
a first memory die (die 150d1 in [0077] and Annotated Fig. 2D, hereinafter, first memory die 150d1), disposed over the first front-side RDL1d (Annotated Fig. 2D shows die structure 150' containing first memory die 150d1 disposed over the first front-side RDL1d);
a second memory die (die 150d2 in [0077] and Annotated Fig. 2D, hereinafter, second memory die 150d2), disposed over the first front-side RDL1d (Annotated Fig. 2D shows die structure 150' containing second memory die 150d2 disposed over the first front-side RDL1d), wherein the first memory die 150d1 and the second memory die 150d2 are horizontally arranged (Annotated Fig. 2D shows first memory die 150d1 and second memory die 150d2 horizontally arranged inside die structure 150');
a first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D), disposed over the first front-side RDL1d between the first memory die 150d1 and the second memory die 150d2 (Annotated Fig. 2D shows the first interconnect die disposed over the first front-side RDL1d between first memory die 150d1 and second memory die 150d2), wherein the first memory die 150d1 is electrically connected to a first via (labeled “first via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, first memory die 150d1 electrically connected to TIV 153d through the first front-side RDL1d in [0077], and Annotated Fig. 2D shows first memory die 150d1 electrically connected to first via first front-side RDL1d), and second memory die 150d2 is electrically connected to a second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, second memory die 150d2 electrically connected to TIV 153d through the first front-side RDL1d in [0077], and Annotated Fig. 2D shows second memory die 150d2 electrically connected to second via);
a first molding material layer (first molding material layer (i.e. wherein the encapsulant is known in the art to serve as a molding material) in Annotated Fig. 2D) formed in a space between the first memory die 150d1 and the first interconnect die (first molding material layer is shown as a portion of the encapsulant 151d and laterally encapsulates a sidewall of the first memory die 150d1 and a sidewall of the first interconnect die, [0071], Annotated Fig. 2D); and
a second molding material layer (second molding material layer (i.e. wherein the encapsulant is known in the art to serve as a molding material) in Annotated Fig. 2D) formed in a space between the second memory die 150d2 and the first interconnect die (second molding material layer is shown as a portion of the encapsulant 151d and laterally encapsulates a sidewall of the second memory die 150d2 and a sidewall of the first interconnect die, [0071], Annotated Fig. 2D);
wherein the first molding material layer separates the first interconnect die from the first memory die 150d1 (first interconnect die and first memory die 150d1 are separated by the first molding material layer as shown in Annotated Fig. 2D);
wherein the second molding material layer separates the first interconnect die from the second memory die 150d2 (first interconnect die and second memory die 150d2 are separated by the second molding material layer);
wherein the first front-side RDL1d, the first memory die 150d1, the second memory die 150d2 and the first interconnect die are disposed in a first reconstructed chip (encapsulant formed from polymer layers PM1d and PM2c, and outer lateral encapsulant 151d - labeled “first reconstructed chip” in Annotated Fig. 2D).
Tsai does not explicitly disclose the semiconductor structure, wherein the first interconnect die comprises a first substrate layer having a front surface and a back surface;
wherein the first molding material layer is formed between the first memory die and the first substrate layer to separate the first interconnect die from the first memory die;
wherein the second molding material layer is formed between the second memory die and the first substrate layer to separate the first interconnect die from the second memory die; and
wherein the first via and the second via are extended through the first substrate layer from the front surface to the back surface.
However, Yu discloses a semiconductor structure wherein a first interconnect die (first interconnect die in Annotated Fig. 4) comprises a first substrate layer (semiconductor substrate 22, hereinafter first substrate layer 22, [0040], Annotated Fig. 4) having a front surface and a back surface (front surface of first substrate layer 22 and back surface of first substrate layer 22 in Annotated Fig. 4);
wherein a first via and a second via are extended through the first substrate layer from the front surface to the back surface (first via and second via both extend through the first substrate layer 22 from the front surface of first substrate layer 22 to the back surface of first substrate layer 22 in Annotated Fig. 4).
Given the evolving need for more input/output pads on dies for greater parallel processing capabilities despite the decrease in area available for those pads to occupy, one of ordinary skill in the art would be motivated to increase the density of those pads ([0002]) and therefore TIVs by forming the interconnect dies with TIVs extending through a semiconductor substrate instead of a molding material because the semiconductor substrate supports smaller, more precisely placed, and vertically integrated interconnects, while the molding material’s properties constrain via size and placement.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Tsai with the invention disclosed by Yu by forming the interconnect dies with TIVs extending through a semiconductor substrate instead of a molding material to improve TIV density.
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Claim 2, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 1.
Tsai further discloses wherein the first memory die 150d1 is electrically connected to the first via (labeled “first via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) through the first front-side RDL1d (first front-side RDL1d in physical and electrical contact with first memory die 150d1 and the TIVs 153d [0076], Annotated Fig. 2D shows the first front-side RDL1d in contact with the first memory die 150d1 and the first via).
Claim 3, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 1.
Tsai further discloses wherein the second memory die 150d2 is electrically connected to the second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) through the first front-side RDL1d (first front-side RDL1d in physical and electrical contact with second memory die 150d2 and the TIVs 153d [0076], Annotated Fig. 2D shows the first front-side RDL1d in contact with the second memory die 150d2 and the second via).
Claim 4, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 1.
Tsai further discloses wherein the first memory die 150d1 and the second memory die 150d2 individually are electrically connected to the logic wafer 112 through the first front-side RDL1d (the first memory die 150d1 and the second memory die 150d2 are electrically connected to the first front-side RDL1d which is further electrically connected to RDL structure 132 and therefore electrically connected to logic wafer 112 [0077], and Annotated Fig. 2D).
Claim 7, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 1.
Tsai further discloses the semiconductor structure S5 according to claim 1, further comprising:
a second reconstructed chip (encapsulant formed from polymer layers PM1c and PM2b, and lateral encapsulant 151c - labeled “second reconstructed chip” in Annotated Fig. 2D), disposed over the first reconstructed chip (Annotated Fig. 2D shows second reconstructed chip disposed over first reconstructed chip), wherein the second reconstructed chip (labeled “second reconstructed chip” in Annotated Fig. 2D) includes:
a second front-side RDL (redistribution layer RDL1c in [0077], hereinafter, second front-side RDL1c), disposed over and electrically connected to the first reconstructed chip (the TIV 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the second front-side RDL1c [0075], and Annotated Fig. 2D shows the second front-side RDL1c disposed over the first reconstructed chip);
a third memory die (die 150c1 in [0077] and Annotated Fig. 2D, hereinafter, third memory die 150c1), disposed over the second front-side RDL1c (Annotated Fig. 2D shows the third memory die 150c1 disposed over the second front-side RDL1c);
a fourth memory die (die 150c2 in [0077] and Annotated Fig. 2D, hereinafter, fourth memory die 150c2), disposed over the second front-side RDL1c (Annotated Fig. 2D shows the fourth memory die 150c2 disposed over the second front-side RDL1c), wherein the third memory die 150c1 and the fourth memory die 150c2 are horizontally arranged (Annotated Fig. 2D shows the third memory die 150c1 and fourth memory die 150c2 horizontally arranged);
a second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D), disposed over the second front-side RDL1c between the third memory die 150c1 and the fourth memory die 150c2 (Annotated Fig. 2D shows the second interconnect die disposed over the second front-side RDL1c between third memory die 150c1 and fourth memory die 150c2), wherein the third memory die 150c1 is electrically connected to a third via (labeled “third via” in Annotated Fig. 2D) in the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D, Annotated Fig. 2D shows the second front-side RDL1c in contact with the third memory die 150c1 and the third via), and the fourth memory die 150c2 is electrically connected to a fourth via (labeled “fourth via” in Annotated Fig. 2D) in the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D, Annotated Fig. 2D shows the second front-side RDL1c in contact with the fourth memory die 150c2 and the fourth via);
a third molding material layer (third molding material layer (i.e. wherein the encapsulant is known in the art to serve as a molding material) in Annotated Fig. 2D) formed in a space between the third memory die 150c1 and the second interconnect die (third molding material layer is shown as a portion of the encapsulant 151c and laterally encapsulates a sidewall of the third memory die 150c1 and a sidewall of the second interconnect die, [0070], Annotated Fig. 2D); and
a fourth molding material layer (third molding material layer (i.e. wherein the encapsulant is known in the art to serve as a molding material) in Annotated Fig. 2D) formed in a space between the fourth memory die 150c2 and the second interconnect die (fourth molding material layer is shown as a portion of the encapsulant 151c and laterally encapsulates a sidewall of the fourth memory die 150c2 and a sidewall of the second interconnect die, [0070], Annotated Fig. 2D).
Tsai does not explicitly disclose wherein the third molding material layer is formed between the third memory die 150c1 and a second substrate layer to separate the second interconnect die from the third memory die 150c1; and
wherein the fourth molding material layer is formed between the fourth memory die 150c2 and the second substrate layer to separate the second interconnect die from the fourth memory die 150c2.
However, Yu discloses a semiconductor structure wherein a second interconnect die (second interconnect die in Annotated Fig. 4) comprises a second substrate layer (semiconductor substrate 62, hereinafter second substrate layer 62, [0042], Annotated Fig. 4).
Given the evolving need for more input/output pads on dies for greater parallel processing capabilities despite the decrease in area available for those pads to occupy, one of ordinary skill in the art would be motivated to increase the density of those pads ([0002]) and therefore TIVs by forming the interconnect dies with TIVs extending through a semiconductor substrate instead of a molding material because the semiconductor substrate supports smaller, more precisely placed, and vertically integrated interconnects, while the molding material’s properties constrain via size and placement.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Tsai with the invention disclosed by Yu by forming the interconnect dies with TIVs extending through a semiconductor substrate instead of a molding material to improve TIV density.
Claim 11, the combination of Tsai and Yu discloses the semiconductor structure S5 of claim 7.
Tsai further discloses wherein the first via and the second via penetrate through the first interconnect die (the TIVs 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the redistribution layer RDL1c [0075], and Annotated Fig. 2D shows the first via and the second via penetrating through the first interconnect die).
Tsai does not explicitly disclose wherein the second interconnect die comprises the second substrate layer having a front surface and a back surface;
wherein the third via and the fourth via are extended into the second substrate layer from the front surface toward the back surface, such that the third via and the fourth via stop within the second substrate layer of the second interconnect die.
However, Yu discloses a semiconductor structure wherein a second interconnect die (second interconnect die in Annotated Fig. 4) comprises the second substrate layer (semiconductor substrate 62, hereinafter second substrate layer 62, [0042], Annotated Fig. 4) having a front surface and a back surface (front surface of second substrate layer 62 and back surface of second substrate layer 62 in Annotated Fig. 4);
wherein a third via and a fourth via are extended into the second substrate layer from the front surface to the back surface (third via and fourth via both extend through the second substrate layer 62 from the front surface of second substrate layer 62 to the back surface of second substrate layer 62 such that the third via and the fourth via stop within the second substrate layer 62 of the second interconnect die in Annotated Fig. 4).
The combination of the conductive vias not being revealed from the back surface of the substrate layer 62 in Annotated Fig. 4 in Yu and the semiconductor structure S5 according to claim 7 disclosed by Tsai would yield the predictable result of providing electrical connectivity to the upper-most layer of the semiconductor structure S5 while preventing further layers from being added on without further processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure S5 according to claim 7 and disclosed by Tsai, to embed the third via (labeled “third via” in Annotated Fig. 2D) and the fourth via (labeled “fourth via” in Annotated Fig. 2D) so that they will not be revealed on the back surface of the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D).
Claim 13, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 7.
Tsai further discloses wherein the third memory die 150c1 is electrically connected to the logic wafer 112 through the first via (labeled “first via” in Annotated Fig. 2D) or the second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, the first front-side RDL1d is in contact with RDL structure 132 which is electrically connected to logic wafer 112 [0056], and Annotated Fig. 2D shows the second front-side RDL1c in contact with the third memory die 150c1 and the first via, and the first via in contact with the first front-side RDL1d).
Claim 14, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 7.
Tsai further discloses wherein the third memory die 150c1 and the first memory die 150d1 are vertically aligned (Annotated Fig. 2D shows the first memory die 150d1 vertically aligned with the third memory die 150c1).
Claim 15, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 7.
Tsai further discloses wherein the fourth memory die 150c2 and the second memory die 150d2 are vertically aligned (Annotated Fig. 2D shows the second memory die 150d2 vertically aligned with the fourth memory die 150c2).
Claim 16, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 7.
Tsai further discloses wherein the first interconnect die and the second interconnect die are vertically aligned (Annotated Fig. 2D shows the first interconnect die vertically aligned with the second interconnect die) while the first molding material layer and the second molding material layer are vertically aligned with the third molding material layer and the fourth molding material layer respectively (Annotated Fig. 2D shows the first molding material layer being vertically aligned with the third molding material layer and the second molding material layer being vertically aligned with the fourth molding material layer).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Yu further in view of HUNT. (US 20120119373 A1).
Claim 5, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 1.
Tsai further discloses wherein the first via (labeled “first via” in Annotated Fig. 2D) and the second via (labeled “second via” in Annotated Fig. 2D) penetrate through the first interconnect die (the TIV 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the redistribution layer RDL1c [0075], and Annotated Fig. 2D shows the first via and the second via penetrating through the first interconnect die);
wherein a top surface of the first via and a top surface of the second via are coplanar (a top surface of the first via and a top surface of the second via appear coplanar in Annotated Fig. 2D);
wherein a top surface of the first molding material layer and a top surface of the second molding material layer are coplanar (a top surface of the first molding material layer and a top surface of the second molding material layer appear coplanar in Annotated Fig. 2D);
wherein a bottom surface of the first via, a bottom surface of the second via, a bottom surface of the first molding material layer, and a bottom surface of the second molding material layer are coplanar (the bottom surfaces of the TIVs 153d, comprising the first via and second via, are substantially coplanar with the bottom surface of the encapsulant 151d, comprising the first molding material layer and the second molding material layer, [0071]).
Tsai does not explicitly disclose wherein a top surface of the first via, a top surface of the second via, a top surface of the first molding material layer, a top surface of the second molding material layer, and the back surface of the first substrate layer are coplanar;
wherein a bottom surface of the first via, a bottom surface of the second via, a bottom surface of the first molding material layer, a bottom surface of the second molding material layer, and the front surface of the first substrate layer are coplanar.
However, Yu discloses a semiconductor structure wherein a top surface of a first via, a top surface of a second via, and a back surface of a first substrate layer are coplanar (Annotated Fig. 4 shows a top surface of first via, a top surface of second via, and a back surface of first substrate layer 22 being coplanar);
wherein a bottom surface of the first via, a bottom surface of the second via, and a front surface of the first substrate layer are coplanar (Annotated Fig. 4 shows a bottom surface of first via, a bottom surface of second via, and a front surface of first substrate layer 22 being coplanar).
Having all of the device components and adjacent structures including the surrounding molding material share the same surface, which can be achieved with one of many known planarization processes (Yu, [0078]), enables the devices to be stacked in a way that improves alignment, allows for denser via arrays in the interconnect structures, decreases the overall device size, and simplifies the assembly process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of Tsai and Yu with the invention taught by Yu by performing a planarization process on the interconnect dies and surrounding molding material in order to enable the devices to be stacked in a way that improves alignment, allow for denser via arrays in the interconnect structures, decrease the overall device size, and simplify the assembly process.
The combination of Tsai and Yu does not explicitly disclose wherein a top surface of the first via, a top surface of the second via, a top surface of the first molding material layer, a top surface of the second molding material layer, and the back surface of the first substrate layer are coplanar.
However HUNT discloses a top surface of a first via (first via in Annotated Fig. 8E; conductive via 174B in Fig. 1), a top surface of a second via (second via in Annotated Fig. 8E; conductive via 174A in Fig. 1), a top surface of a first molding material layer (first molding material layer in Annotated Fig. 8E; package body 114 is formed from a molding material and shares upper surface 173, [0022], Fig. 1), a top surface of a second molding material layer (second molding material in Annotated Fig. 8E; package body 114 is formed from a molding material and shares upper surface 173, [0022], Fig. 1), and the back surface of a first substrate layer (back surface of interposers in Annotated Fig. 8E; each interposer 170 is comprised of a substrate material and therefore comprises a substrate layer [0023]; upper surface 173 shares a surface with interposers 170A and 170B in Fig. 1) are coplanar (a portion of each interposer 870 is removed to form the interposers 170, along with a portion of the molding material by a technique resulting in a substantially coplanar surface 832, [0058], Annotated Fig. 8E).
Having all of the device components and adjacent structures including the surrounding molding material share the same surface, which can be achieved with one of many known planarization processes (Yu, [0078]), enables the devices to be stacked in a way that improves alignment, allows for denser via arrays in the interconnect structures, decreases the overall device size, and simplifies the assembly process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of Tsai and Yu with the invention taught by Yu by performing a planarization process on the interconnect dies and surrounding molding material in order to enable the devices to be stacked in a way that improves alignment, allow for denser via arrays in the interconnect structures, decrease the overall device size, and simplify the assembly process.
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Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Yu further in view of HUNT further in view of Tong. Et al. (US 20240128208 A1).
Claim 6, the combination of Tsai, Yu, and HUNT teaches the semiconductor structure S5 according to claim 5.
The combination of Tsai, Yu, and HUNT does not explicitly teach a thickness of the first interconnect die being in a range of 30 to 70 microns.
However, Tong discloses conventional thicknesses of integrated circuit (IC) devices (142D, 142E, and 142F, in [0144]) that fall in the range of 30-775 microns. The device thickness is a result effective variable as one would have chosen the thickness of an IC device by balancing the need for reducing a device size to increase the compactness of the device with the need to retain IC device function. One skilled in the art would have been motivated to produce an IC device in the claimed range balancing the desired effectiveness of reducing the device size while maintaining device function.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Tsai with the claimed range disclosed by Tong as it would merely result in an optimization of a result effective variable.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Yu further in view of Das. Et al. (US 20170040296 A1).
Claim 12, the combination of Tsai and Yu discloses the semiconductor structure S5 of claim 7.
The combination of Tsai and Yu does not explicitly disclose wherein a thickness of the first substrate layer of the first interconnect die is less than a thickness of the second substrate layer of the second interconnect die.
However, Das discloses wherein a thickness of a first substrate layer of a first interconnect die is less than a thickness of a second substrate layer of a second interconnect die (second silicon layer 180 can have a thickness less than a thickness of first silicon layer 110, [0127], Fig. 1B; first silicon layer 110 includes TSV structures 114 and is therefore analogous to an interconnect die, [0088], Fig. 1B; second silicon layer 180 includes TSV structures 186 and is therefore analogous to an interconnect die, [0125], Fig. 1B).
Having intentional thickness variations across layers for different device functions and therefore different device components with unequal thicknesses would allow different semiconductor die to be interchanged in the semiconductor package and allow the package to be used for a wider variety of applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Tsai with the unequal thicknesses of Das to accommodate the use of the different device types which would increase flexibility in the overall device design and usage.
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Das Fig. 1B
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Yu further in view of YOU. Et al. (US 20230133977 A1).
Claim 8, the combination of Tsai and Yu discloses the semiconductor structure S5 according to claim 7.
The combination of Tsai and Yu does not explicitly disclose a first backside RDL, disposed over the first memory die 150d1, the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D), and the second memory die 150d2, wherein the second front-side RDL1c is electrically connected to the first backside RDL.
However, YOU discloses a first backside RDL (first upper redistribution layer PRDL1 in [0021] and Fig. 1 from YOU, hereinafter, first backside RDL PRDL1), disposed over a first core semiconductor stack (first core semiconductor stack CST1 in [0021], [0049], and Fig. 1 from YOU, hereinafter first core semiconductor stack CST1), and a memory semiconductor stack (memory semiconductor stack MST1 in [0021], [0049], and Fig. 1 from YOU, hereinafter, memory semiconductor stack MST1) disposed over a first front-side RDL (first lower redistribution layer NRDL1 in [0021] and Fig. 1 from YOU, hereinafter, first front-side RDL NRDL1), wherein the first backside RDL PRDL1 electrically connected to a first second front-side RDL (lower redistribution layer NRDL2, in [0021] and Fig 1, hereinafter, second front-side RDL NRDL2, electrically connected to the first backside RDL PRDL1 in [0054]). The placement of the upper redistribution layer provides more possible connections and routing avenues between the core semiconductor stacks and the semiconductor memory stacks of the packages.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a backside redistribution layer to each tier (T4 and T3 in Annotated Fig. 2D) in order to establish connections between the first memory die 150d1 and the second memory die 150d2, increase interconnection density between the tiers, and aid in routing efficiency and flexibility in the device design.
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Fig. 1 (YOU) – illustrates a first backside RDL PRDL1 including first upper lines PIL1 and a first upper dielectric layer PIN1, a second front-side RDL NRDL2 including second lower lines NIL2 and the second lower dielectric layer NIN2, a first front-side RDL NRDL1, a first core semiconductor stack CST1, and a memory semiconductor stack MST1.
Claim 10, the combination of Tsai, Yu, and YOU teaches the semiconductor structure S5 according to claim 8.
YOU further discloses that the first backside RDL PRDL1 may include first upper lines PIL1, hereinafter, first upper lines PIL1, and a first upper dielectric layer PIN1, hereinafter, first upper dielectric layer PIN1 in [0047], the second front-side RDL NRDL2 may include second lower lines NIL2, hereinafter, second lower lines NIL2, and a second lower dielectric layer NIN2, hereinafter, second lower dielectric layer NIN2 in [0051], and that one (or more) of the second lower lines NIL2 may be electrically connected to uppermost first upper lines PIL1 of the first [backside RDL] PRDL1” [0054].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Yu further in view of YOU as applied to claim 8 above, and further in view of Yang. (US 20080157316 A1).
Claim 9, the combination of Tsai, Yu, and YOU teaches the semiconductor structure S5 according to claim 8.
The combination of Tsai, Yu, and YOU does not explicitly disclose the second front-side RDL1c or NRDL2 being electrically connected to the first backside RDL PRDL1 through conductive bumps.
However, Yang discloses a front-side RDL (RDL 34 in [0024] and Fig. 1 from Yang) and a backside RDL (RDL 24 in [0024] and Fig. 1 from Yang) being coupled to conductive bumps (conductive bumps 40 in [0024] and Fig. 1 from Yang). Yang teaches the use of conductive bumps for coupling the contact pads of first RDL and the contact pads of second RDL in [0008]. The usage of conductive bumps to couple the contact pads of the first RDL and the contact pads of the second RDL provides higher mechanical and thermal stress handling, lower manufacturing costs and complexity, and higher surface topology tolerance compared to alternative methods such as hybrid bonding and through-silicon vias.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to electrically connect the second front-side RDL1c or NRDL2 and the first backside RDL PRDL1 by coupling their contact pads as taught by Yang in order to achieve a higher manufacturing yield, lower manufacturing cost, and less stress between the RDLs.
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Fig. 1 (Yang) – illustrates a RDL 34 and a RDL 24 being coupled to conductive bumps 40.
Response to Arguments
Applicant’s arguments, see page 1 lines 1-11 of amendments to the Specification, filed on September 3, 2026, with respect to the Specification have been fully considered and are persuasive. The objection of reference characters "22" in [0038], [0039], [0055]-[0058], [0065], [0067], and [0070], and "25" in [0027] being used to designate via structures has been withdrawn.
Applicant’s arguments, see pages 10-17, filed September 3, 2026, with respect to the rejection(s) of claim(s) 1-16 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tsai in view of Yu.
In regards to claim 1:
Applicant argues that Tsai fails to anticipate that "a first molding material layer 41 formed a space between the first memory die and the first interconnect die" and "a second molding material layer 41 formed a space between the second memory die and the first interconnect die" (see Remarks at pages 10-11). The Examiner respectfully disagrees. Tsai may not explicitly disclose a molding material layer but Tsai discloses encapsulants 151a-151d and further specifies in [0068]-[0071] that they laterally encapsulate the sidewalls of the dies 150a1-150d2 and TIVs 153a-153d and therefore can be molding material layers. In addition, Tsai discloses multiple embodiments (Fig. 2D among them) that shows the encapsulants separating the memory dies from the interconnects (TIVs disposed in molding material). Therefore, applicants arguments are not persuasive.
Applicant argues that Tsai fails to anticipate "a first substrate layer 21 having a front surface 102A and a back surface 102B" and "the first via and the second via are extended through the first substrate layer from the front surface to the back surface". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
Applicant argues that Tsai fails to anticipate that "the first molding material layer 41 is formed between the first memory die and the first substrate layer 21 to separate the first interconnect die from the first memory die" and "the second molding material layer 41 is formed between the second memory die and the first substrate layer 21 to separate the first interconnect die from the second memory die". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
In regards to claim 5:
Applicant argues that Tsai fails to anticipate that "a top surface of the first via, a top surface of the second via, a top surface of the first molding material layer, a top surface of the second molding material layer, and the back surface 102B of the first substrate layer 21 are coplanar" and "a bottom surface of the first via, a bottom surface of the second via, a bottom surface of the first molding material layer, a bottom surface of the second molding material layer, and the front surface 102B of the first substrate layer 21 are coplanar". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
In regards to claim 7:
Applicant argues that Tsai fails to anticipate that "a third molding material layer 41 formed a space between the third memory die and the second interconnect die" and "a fourth molding material layer 41 formed a space between the fourth memory die and the second interconnect die". The Examiner respectfully disagrees. Tsai may not explicitly disclose a molding material layer but Tsai discloses encapsulants 151a-151d and further specifies in [0068]-[0071] that they laterally encapsulate the sidewalls of the dies 150a1-150d2 and TIVs 153a-153d and therefore can be molding material layers. In addition, Tsai discloses multiple embodiments (Fig. 2D among them) that shows the encapsulants separating the memory dies from the interconnects (TIVs disposed in molding material). Therefore, applicants arguments are not persuasive.
Applicant argues that Tsai fails to anticipate that "the third molding material layer 41 is formed between the third memory die and the second substrate layer 21 to separate the second interconnect die from the third memory die" and "the fourth molding material layer 41 is formed between the fourth memory die and the second substrate layer 21 to separate the second interconnect die from the fourth memory die". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
In regards to claim 16:
Applicant argues that Tsai fails to anticipate that "the first molding material layer and the second molding material layer are vertically aligned with the third molding material layer and the fourth molding material layer respectively". The Examiner respectfully disagrees. Tsai may not explicitly disclose a molding material layer but Tsai discloses encapsulants 151a-151d and further specifies in [0068]-[0071] that they laterally encapsulate the sidewalls of the dies 150a1-150d2 and TIVs 153a-153d and therefore can be molding material layers. In addition, Tsai discloses multiple embodiments (Fig. 2D among them) that shows the encapsulants separating the memory dies from the interconnects (TIVs disposed in molding material). Therefore, applicants arguments are not persuasive.
Applicant respectfully submits that since the first memory die and the second memory are vertically aligned with the third memory die and the fourth memory die respectively while the first interconnect die and the second interconnect die are vertically aligned, the first molding material layer and the second molding material layer will be vertically aligned with the third molding material layer and the fourth molding material layer respectively. The Examiner accepts that statement.
In regards to claim 11:
Applicant argues that Tsai fails to anticipate "a second substrate layer having a front surface and a back surface" and "the third via and the fourth via are extended into the second substrate layer from the front surface toward the back surface, such that the third via and the fourth via stop within the second substrate layer of the second interconnect die". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
In regards to claim 12:
Applicant argues that Tsai fails to anticipate that "a thickness of the first substrate layer of the first interconnect die is less than a thickness of the second substrate layer of the second interconnect die". Applicant’s arguments are persuasive. Thus, the newly added limitations have been addressed in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai. Et al. (US 20210305226 A1) further discloses a semiconductor structure analogous to the claimed device comprising a first interconnect die and second interconnect die further comprising a first substrate layer and second substrate layer wherein the first substrate layer has a thickness less than the thickness of the second substrate layer (See Fig. 1F).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL M VANYO/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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