DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on April 2, 2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because the NPL reference 3 combines two translated documents when they should each be attached to their original non-translated document and submitted as a single document. Further, the application number of one of the foreign references it purports to translate (Application number 114105155) does not match the application number cited on the information disclosure statement (Taiwanese Application No. 114105166). Therefore, since NPL reference 3 is not being considered, neither NPL references 1 or 2 are being considered because neither have a certified English translation or a concise statement of relevance as required by MPEP 609.01. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "102d" in [0077] and "103d" in [0030] - [0032], and [0081] have both been used to designate second memory die. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "101c" in [0081] and "103c" in [0030]-[0032], [0077], and [0081] have both been used to designate second memory die. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "22" in [0038], [0039], [0055]-[0058], [0065], [0067], and [0070], and "25" in [0027] have both been used to designate via structures. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “61a” has been used to designate both RDL in [0036] and [0037] and front-side RDL in [0029], [0031], [0032], [0080], and [0081]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “101c” has been used to designate both first memory die in [0030]-[0032], [0077], and [0080] and second memory die in [0081]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “102d” has been used to designate second memory die in [0077], an interconnect die in [0030]-[0032] and [0077], and via structure in [0080] and [0081]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “102b” in [0030]-[0032] and “102c” in [0030]-[0032] and [0077] have been used to designate an interconnect die. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “102b” and “102c” have been used to designate via structure in [0080] and [0081]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the second die" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret “the second die” as “the second memory die”
The term “substantially less” in claim 12 is a relative term which renders the claim indefinite. The term “substantially less” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, “a thickness of the first interconnect die” and “a thickness of the second interconnect die” are both indefinite.
For purposes of examination, the Examiner will interpret “substantially less” as “less.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai. Et al. (US 20210305226 A1).
Claim 1, Tsai discloses a semiconductor structure (semiconductor structure S5 in [0083] and Annotated Fig. 2D, hereinafter, semiconductor structure S5), comprising;
a logic wafer (logic wafer 112 in [0012] and Annotated Fig. 2D, hereinafter, logic wafer 112);
a first front-side redistribution layer (RDL), (redistribution layer RDL1d in [0089] and Annotated Fig. 2D, hereinafter, first front-side RDL1d) disposed over logic wafer 112 (the first front-side RDL1d disposed between the logic wafer 112 and the die stack structure 150' in [0089] and Annotated Fig. 2D);
a first memory die (die 150d1 in [0077] and Annotated Fig. 2D, hereinafter, first memory die 150d1), disposed over the first front-side RDL1d (Annotated Fig. 2D shows die structure 150' containing first memory die 150d1 disposed over the first front-side RDL1d);
a second memory die (die 150d2 in [0077] and Annotated Fig. 2D, hereinafter, second memory die 150d2), disposed over the first front-side RDL1d (Annotated Fig. 2D shows die structure 150' containing second memory die 150d2 disposed over the first front-side RDL1d), wherein the first memory die 150d1 and the second memory die 150d2 are horizontally arranged (Annotated Fig. 2D shows first memory die 150d1 and second memory die 150d2 horizontally arranged inside die structure 150');
and a first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D), disposed over the first front-side RDL1d between the first memory die 150d1 and the second memory die 150d2 (Annotated Fig. 2D shows the first interconnect die disposed over the first front-side RDL1d between first memory die 150d1 and second memory die 150d2), wherein the first memory die 150d1 is electrically connected to a first via (labeled “first via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, first memory die 150d1 electrically connected to TIV 153d through the first front-side RDL1d in [0077], and Annotated Fig. 2D shows first memory die 150d1 electrically connected to first via first front-side RDL1d), and second memory die 150d2 is electrically connected to a second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, second memory die 150d2 electrically connected to TIV 153d through the first front-side RDL1d in [0077], and Annotated Fig. 2D shows second memory die 150d2 electrically connected to second via).
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Annotated Fig. 2D (Tsai)
Claim 2, Tsai discloses the semiconductor structure S5 according to claim 1, wherein the first memory die 150d1 is electrically connected to the first via (labeled “first via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) through the first front-side RDL1d (first front-side RDL1d in physical and electrical contact with first memory die 150d1 and the TIVs 153d [0076], Annotated Fig. 2D shows the first front-side RDL1d in contact with the first memory die 150d1 and the first via).
Claim 3, Tsai discloses the semiconductor structure S5 according to claim 1, wherein the second memory die 150d2 is electrically connected to the second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) through the first front-side RDL1d (first front-side RDL1d in physical and electrical contact with second memory die 150d2 and the TIVs 153d [0076], Annotated Fig. 2D shows the first front-side RDL1d in contact with the second memory die 150d2 and the second via).
Claim 4, Tsai discloses the semiconductor structure S5 according to claim 1, wherein the first memory die 150d1 and the second memory die 150d2 individually are electrically connected to the logic wafer 112 through the first front-side RDL1d (the first memory die 150d1 and the second memory die 150d2 are electrically connected to the first front-side RDL1d which is further electrically connected to RDL structure 132 and therefore electrically connected to logic wafer 112 [0077], and Annotated Fig. 2D).
Claim 5, Tsai discloses the semiconductor structure S5 according to claim 1, wherein the first via (labeled “first via” in Annotated Fig. 2D) and the second via (labeled “second via” in Annotated Fig. 2D) penetrate through the first interconnect die (the TIV 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the redistribution layer RDL1c [0075], and Annotated Fig. 2D shows the first via and the second via penetrating through the first interconnect die).
Claim 7, Tsai discloses the semiconductor structure S5 according to claim 1, wherein the first front-side RDL1d, the first memory die 150d1, the second memory die 150d2 and the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) are disposed in a first reconstructed chip (encapsulant formed from polymer layers PM1d and PM2c, and lateral encapsulant 151d - labeled “first reconstructed chip” in Annotated Fig. 2D), and the semiconductor structure S5 further comprises:
a second reconstructed chip (encapsulant formed from polymer layers PM1c and PM2b, and lateral encapsulant 151c - labeled “second reconstructed chip” in Annotated Fig. 2D), disposed over the first reconstructed chip (Annotated Fig. 2D shows second reconstructed chip disposed over first reconstructed chip), wherein the second reconstructed chip (labeled “second reconstructed chip” in Annotated Fig. 2D) includes:
a second front-side RDL (redistribution layer RDL1c in [0077], hereinafter, second front-side RDL1c), disposed over and electrically connected to the first reconstructed chip (the TIV 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the second front-side RDL1c [0075], and Annotated Fig. 2D shows the second front-side RDL1c disposed over the first reconstructed chip);
a third memory die (die 150c1 in [0077] and Annotated Fig. 2D, hereinafter, third memory die 150c1), disposed over the second front-side RDL1c (Annotated Fig. 2D shows the third memory die 150c1 disposed over the second front-side RDL1c);
a fourth memory die (die 150c2 in [0077] and Annotated Fig. 2D, hereinafter, fourth memory die 150c2), disposed over the second front-side RDL1c (Annotated Fig. 2D shows the fourth memory die 150c2 disposed over the second front-side RDL1c), wherein the third memory die 150c1 and the fourth memory die 150c2 are horizontally arranged (Annotated Fig. 2D shows the third memory die 150c1 and fourth memory die 150c2 horizontally arranged); and
a second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D), disposed over the second front-side RDL1c between the third memory die 150c1 and the fourth memory die 150c2 (Annotated Fig. 2D shows the second interconnect die disposed over the second front-side RDL1c between third memory die 150c1 and fourth memory die 150c2), wherein the third memory die 150c1 is electrically connected to a third via (labeled “third via” in Annotated Fig. 2D) in the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D, Annotated Fig. 2D shows the second front-side RDL1c in contact with the third memory die 150c1 and the third via), and the fourth memory die 150c2 is electrically connected to a fourth via (labeled “fourth via” in Annotated Fig. 2D) in the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D, Annotated Fig. 2D shows the second front-side RDL1c in contact with the fourth memory die 150c2 and the fourth via).
Claim 13, Tsai discloses the semiconductor structure S5 according to claim 7, wherein the third memory die 150c1 is electrically connected to the logic wafer 112 through the first via (labeled “first via” in Annotated Fig. 2D) or the second via (labeled “second via” in Annotated Fig. 2D) in the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D, the first front-side RDL1d is in contact with RDL structure 132 which is electrically connected to logic wafer 112 [0056], and Annotated Fig. 2D shows the second front-side RDL1c in contact with the third memory die 150c1 and the first via, and the first via in contact with the first front-side RDL1d).
Claim 14, Tsai discloses the semiconductor structure S5 according to claim 7, wherein the third memory die 150c1 and the first memory die 150d1 are vertically aligned (Annotated Fig. 2D shows the first memory die 150d1 vertically aligned with the third memory die 150c1).
Claim 15, Tsai discloses the semiconductor structure S5 according to claim 7, wherein the fourth memory die 150c2 and the second memory die 150d2 are vertically aligned (Annotated Fig. 2D shows the second memory die 150d2 vertically aligned with the fourth memory die 150c2).
Claim 16, Tsai discloses the semiconductor structure S5 according to claim 7, wherein the first interconnect die and the second interconnect die are vertically aligned (Annotated Fig. 2D shows the first interconnect die vertically aligned with the second interconnect die).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Tong. Et al. (US 20240128208 A1).
Claim 6, Tsai discloses the semiconductor structure S5 according to claim 5.
Tsai does not explicitly disclose a thickness of the first interconnect die being in a range of 30 to 70 microns.
However, Tong discloses conventional thicknesses of integrated circuit (IC) devices (142D, 142E, and 142F, in [0144]) that fall in the range of 30-775 microns. The device thickness is a result effective variable as one would have chosen the thickness of an IC device by balancing the need for reducing a device size to increase the compactness of the device with the need to retain IC device function. One skilled in the art would have been motivated to produce an IC device in the claimed range balancing the desired effectiveness of reducing the device size while maintaining device function.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Tsai with the claimed range disclosed by Tong as it would merely result in an optimization of a result effective variable.
Claim 12, Tsai discloses the semiconductor structure S5 of claim 7.
Tsai does not explicitly disclose a thickness of the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D) being substantially less (“less” for the purpose of examination) than a thickness of the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D).
However, Tong discloses IC structures 142D, 142E, and 142F (Fig. 7J) that are characterized by substantially equal or unequal thicknesses in [0144]; and the semiconductor die, 143A, 143B and 143C, (which are contained within the IC structures 142D, 142E, and 142F respectively as shown in Fig. 7J) that can be at least one of a CPU die, a GPU die, a TPU die, a MEMS die, an AP die, an FPGA die, an ASIC die, a memory die, a transceiver die, a network interface die, an integrated photonics die, a packet buffer/router die or another suitable die (e.g., an interconnect die such as an interposer) in [0139]. Having IC structures with unequal thicknesses would allow different semiconductor die to be interchanged in the semiconductor package and allow the package to be used for a wider variety of applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by Tsai with the unequal thicknesses of Tong in order to accommodate the use of the different device types which would increase flexibility in the overall device design and usage.
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Fig. 7J (Tong) – illustrates semiconductor die 143A, 143B, and 143C disposed in IC structures 142D, 142E, and 142F respectively.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of YOU. Et al. (US 20230133977 A1).
Claim 8, Tsai discloses the semiconductor structure S5 according to claim 7.
Tsai does not explicitly disclose a first backside RDL, disposed over the first memory die 150d1, the first interconnect die (labeled “first interconnect die” in Annotated Fig. 2D), and the second memory die 150d2, wherein the second front-side RDL1c is electrically connected to the first backside RDL.
However, YOU discloses a first backside RDL (first upper redistribution layer PRDL1 in [0021] and Fig. 1 from YOU, hereinafter, first backside RDL PRDL1), disposed over a first core semiconductor stack (first core semiconductor stack CST1 in [0021], [0049], and Fig. 1 from YOU, hereinafter first core semiconductor stack CST1), and a memory semiconductor stack (memory semiconductor stack MST1 in [0021], [0049], and Fig. 1 from YOU, hereinafter, memory semiconductor stack MST1) disposed over a first front-side RDL (first lower redistribution layer NRDL1 in [0021] and Fig. 1 from YOU, hereinafter, first front-side RDL NRDL1), wherein the first backside RDL PRDL1 electrically connected to a first second front-side RDL (lower redistribution layer NRDL2, in [0021] and Fig 1, hereinafter, second front-side RDL NRDL2, electrically connected to the first backside RDL PRDL1 in [0054]). The placement of the upper redistribution layer provides more possible connections and routing avenues between the core semiconductor stacks and the semiconductor memory stacks of the packages.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a backside redistribution layer to each tier (T4 and T3 in Annotated Fig. 2D) in order to establish connections between the first memory die 150d1 and the second memory die 150d2, increase interconnection density between the tiers, and aid in routing efficiency and flexibility in the device design.
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Fig. 1 (YOU) – illustrates a first backside RDL PRDL1 including first upper lines PIL1 and a first upper dielectric layer PIN1, a second front-side RDL NRDL2 including second lower lines NIL2 and the second lower dielectric layer NIN2, a first front-side RDL NRDL1, a first core semiconductor stack CST1, and a memory semiconductor stack MST1.
Claim 10, the combination of Tsai in view of YOU teaches the semiconductor structure S5 according to claim 8.
YOU further discloses that the first backside RDL PRDL1 may include first upper lines PIL1, hereinafter, first upper lines PIL1, and a first upper dielectric layer PIN1, hereinafter, first upper dielectric layer PIN1 in [0047], the second front-side RDL NRDL2 may include second lower lines NIL2, hereinafter, second lower lines NIL2, and a second lower dielectric layer NIN2, hereinafter, second lower dielectric layer NIN2 in [0051], and that one (or more) of the second lower lines NIL2 may be electrically connected to uppermost first upper lines PIL1 of the first [backside RDL] PRDL1” [0054].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of YOU as applied to claim 8 above, and further in view of Yang. (US 20080157316 A1).
Claim 9, the combination of Tsai in view of YOU teaches the semiconductor structure S5 according to claim 8.
The combination of Tsai in view of YOU does not explicitly disclose the second front-side RDL1c or NRDL2 being electrically connected to the first backside RDL PRDL1 through conductive bumps.
However, Yang discloses a front-side RDL (RDL 34 in [0024] and Fig. 1 from Yang) and a backside RDL (RDL 24 in [0024] and Fig. 1 from Yang) being coupled to conductive bumps (conductive bumps 40 in [0024] and Fig. 1 from Yang). Yang teaches the use of conductive bumps for coupling the contact pads of first RDL and the contact pads of second RDL in [0008]. The usage of conductive bumps to couple the contact pads of the first RDL and the contact pads of the second RDL provides higher mechanical and thermal stress handling, lower manufacturing costs and complexity, and higher surface topology tolerance compared to alternative methods such as hybrid bonding and through-silicon vias.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to electrically connect the second front-side RDL1c or NRDL2 and the first backside RDL PRDL1 by coupling their contact pads as taught by Yang in order to achieve a higher manufacturing yield, lower manufacturing cost, and less stress between the RDLs.
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Fig. 1 (Yang) – illustrates a RDL 34 and a RDL 24 being coupled to conductive bumps 40.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Claim 11, Tsai discloses the semiconductor structure S5 according to claim 7, wherein the first via (labeled “first via” in Annotated Fig. 2D) and the second via (labeled “second via” in Annotated Fig. 2D) penetrate through the first interconnect die (the TIV 153d at the fourth tier T4 penetrates through the polymer layer PM2c to be in physical and electrical contact with the redistribution layer RDL1c [0075], and Annotated Fig. 2D shows the first via and the second via penetrating through the first interconnect die).
Tsai does not explicitly disclose the third via (labeled “third via” in Annotated Fig. 2D) and the fourth via (labeled “fourth via” in Annotated Fig. 2D) stopping within the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D).
However, Tsai teaches the conductive vias 136 of the die 150a not being revealed from the back surface of the substrate 135 in [0044] and Annotated Fig. 1F. Both embodiments of the invention taught by Tsai, the semiconductor structure S5 according to claim 7 and Annotated Fig. 1F, are multi-layered semiconductor packing structures capable of compact memory storage. The combination of the conductive vias 136 not being revealed from the back surface of the substrate 135 in Annotated Fig. 1F and the semiconductor structure S5 according to claim 7 and further disclosed by Tsai would yield the predictable result of providing electrical connectivity to the upper-most layer of the semiconductor structure S5 while preventing further layers from being added on without further processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure S5 according to claim 7 and further disclosed by Tsai, to embed the third via (labeled “third via” in Annotated Fig. 2D) and the fourth via (labeled “fourth via” in Annotated Fig. 2D) so that they will not be revealed on the back surface of the second interconnect die (labeled “second interconnect die” in Annotated Fig. 2D).
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Annotated Fig. 1F (Tsai) – illustrates the conductive vias 136 of the die 150a not being revealed from the back surface of the substrate 135.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu. Et al. (US-11282816-B2) discloses multiple embodiments of multilayered packages including multiple encapsulated layers of memory devices disposed over RDLs electrically connected to each other using conductive pillars or vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL M VANYO whose telephone number is (571)270-3088. The examiner can normally be reached 9am-12pm, 1pm-4pm EST Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL M VANYO/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights