Prosecution Insights
Last updated: October 02, 2026
Application No. 18/624,453

TRANSIENT VOLTAGE ABSORPTION ELEMENT

Non-Final OA §112
Filed
Apr 02, 2024
Priority
Oct 04, 2021 — JP 2021-163298 +1 more
Examiner
NGUYEN, CUONG B
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
865 granted / 980 resolved
+28.3% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
46 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
32.2%
-7.8% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 980 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election with traverse of Species I of Fig. 1 (claims 1-20) in the reply filed on July 6th, 2026, is acknowledged. The traversal is on the ground(s) that the Species I and Species II are related inventions and claims 1, 3-6 are generics to both species. This is not found persuasive because all Species I to Species IV are distinct in view of the reasons provided in the previous office action. Although all claims are generic to Fig. 1 and Fig. 8, the restriction must be presented to ensure the Applicant elects one Species for purpose of examination and prior art consideration on the elected Species. If no restriction is made, Applicant can amend claims reciting all Species in Figs. 1 and 8 which would create serious burden for prior art searching and examination. Applicant further traverse on ground that the Office has not shown a serious burden as required by section 803 of MPEP. This is not found persuasive because there is no requirement for identifying different classification, field of search or prior art in section 803 for presenting the reasons on search and/or examination burden in Species restriction. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-12, 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites the limitation “wherein the first buried layer and the second buried layer are separated between the first diode and the second diode adjacent to each other” in lines 15-16. According to Applicant’s disclosure, two separated buried layers BL formed under diode regions, but not between two diode regions (see Fig. 1 and [0032-0040] of Applicant’s specification). Therefore, the above limitation contradicts with the Applicant’s specification. Claims 2-12 are rejected for depending on claim 1 and having the above issues incorporated into the claims. Claim 6 recites the limitation “wherein a portion at which the first buried layer is not formed is present in the inner region”. It is unclear to the examiner how to determine the portion of the first buried layer is not formed when the portion has not been formed. Claim 10 recites the limitation “wherein a portion at which the second buried layer is not formed is present in the inner region”. It is unclear to the examiner how to determine the portion of the second buried layer is not formed when the portion has not been formed. Claim 14 recites the limitation “wherein the first buried layer and the second buried layer are separated between the first diode and the second diode adjacent to each other” in lines 1-3. According to Applicant’s disclosure, two separated buried layers BL formed under diode regions, but not between two diode regions (see Fig. 1 and [0032-0040] of Applicant’s specification). Therefore, the above limitation contradicts with the Applicant’s specification. Claim 19 recites the limitation “wherein a portion at which the first buried layer is not formed is present in the inner region”. It is unclear to the examiner how to determine the portion of the first buried layer is not formed when the portion has not been formed. Allowable Subject Matter Claims 1-12, 14 and 19 would be allowed over prior art of record if amend to overcome the 112 rejections as set forth in the office action above. Claims 13, 15-18 and 20 are allowed over prior art of record. The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: Regarding claims 1 and 13, Mallikarjunaswamy et al. (Patent No.: US 10,062,682 B1) discloses a transient voltage absorption element in Fig. 5 comprising: a semiconductor substrate (50); an epitaxial layer (58) on a surface of the semiconductor substrate, the epitaxial layer including a first p+ region (region 62 in high-side steering diode), a second p+ region (region 62 in low side steering diode), a first n+ region (region 68 in high-side steering diode), and a second n+ region (region 68 in low-side steering diode) formed therein; a first buried layer (left R-PBL) and a second buried layer (right R-PBL) formed within the semiconductor substrate; a first trench (first trench 60) that extends to the first buried layer from a surface side of the epitaxial layer; and a second trench (second trench 60) that extends to the second buried layer from the surface side of the epitaxial layer, wherein a part of the epitaxial layer, the first p+ region, and the first n+ region are surrounded by the first trench and form a first diode, wherein a part of the epitaxial layer, the second p+ region, and the second n+ region are surrounded by the second trench and form a second diode, wherein the first buried layer and the second buried layer are separated between the first diode and the second diode adjacent to each other (separating by trench 60) (see column 6, line 9 through column 8, line 67). Mallikarjunaswamy et al. fails to disclose the first and second buried layers having an impurity concentration that is higher than the semiconductor substrate. Claims 2-12 and 14-20 depend on claims 1 and 13, and therefore also include said claimed limitation. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+15.4%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 980 resolved cases by this examiner. Grant probability derived from career allowance rate.

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