DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. Publication No. US 2014/0198417.
Regarding claims 1, 14, Wang discloses a transient voltage absorption element for being connected to a signal line in series and connected to a shunt between the signal line and a reference potential, the transient voltage absorption element comprising:
a base material [Fig. 7B is disposed on a printed circuit board, and printed circuit board has both a substrate portion and a rewiring portion];
a first input and output terminal [Fig. 7B, Vin] in the base material and connected to the signal line [par. 0051];
a second input and output terminal [Fig. 7B, Vout] in the base material and connected to the signal line [par. 0051];
a reference potential [Fig. 7B, GND terminal] connection terminal in the base material and connected to the reference potential;
an internal signal line that electrically connects the first input and output terminal to the second input and output terminal [Fig. 7B, the signal line on which R1 and R2 are disposed, is connected between Vin and Vout as shown]; and
a surge absorption element [Fig. 7B, diode D3] connected between the internal signal line and the reference potential connection terminal [Fig. 7B, D3 is connected between the internal signal line and GND];
a capacitance component [Fig. 7B, Cp1];
a resistance component [Fig. 7B, R1].
Wang does not explicitly disclose that the magnitude of an impedance of a parasitic capacitance component, in a frequency band of a signal propagating through the internal signal line, is smaller than a resistance component of the internal signal line.
The magnitude of the impedance of a parasitic capacitance to be smaller than the resistance component of the signal line depends on the specific values of the capacitance and resistance elements and the frequency of the signal. It would have been obvious to one having ordinary skill in the art at the time the invention was made to select specific values of capacitor and resistor components such that the magnitude of an impedance of a parasitic capacitance component is smaller than a resistance component of the internal signal line, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 2, 16, Wang discloses that the signal is generated between the first input and output terminal and the second input and output terminal [par. 0051; input signal coming to the input terminal Vin and passes through the filter to the output terminal Vout].
Regarding claims 3, 17, Wang discloses that the internal signal line is a wiring pattern of an electrical conductor having a predetermined resistance component in the base material [Fig. 7B, the conductive pathway/wire (connected between Vin and Vout terminals) has a predetermined resistance].
Regarding claims 4, 18, Wang discloses that the first input and output terminal is directly connected to the second input and output terminal [Fig. 7B, Vin is directly connected to Vout; par. 0051].
Regarding claims 5, 19, Wang discloses that the internal signal line is formed in one layer [the conductive pathway/wire/copper traces is formed in one layer on a printed circuit board], and the parasitic capacitance component is generated on a plane by the wiring pattern [Fig. 7B, capacitor Cp1 is formed on a plane by the wiring pattern on the printed circuit board].
Regarding claim 6, Wang does not disclose that the internal signal line comprises a meandering shape. It would have been an obvious matter of design choice to have the internal signal line in a meandering shape, since applicant has not been disclosed that having a meandering shape signal line solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the straight internal signal line as shown.
Regarding claim 7, Wang discloses that the parasitic capacitance component is generated between the internal signal line and at least one of the first input and output terminal and the second input and output terminal [Fig. 7B, Cp1 is between Vin and Vout terminals].
Regarding claim 8, Wang discloses that the base material further includes a dielectric layer [Fig. 7B is formed on a printed circuit board, and PCB inherently has a substrate portion which is non-conductive dielectric material that provides mechanical support and electrical insulation between the conductive parts], and the internal signal line is disposed at a position that faces at least one of the first input and output terminal and the second input and output terminal with the dielectric layer interposed therebetween [as shown].
Regarding claim 11, Wang discloses that the resistance component and the parasitic capacitance component are generated between the first input and output terminal and the reference potential connection terminal [Fig. 7B, Cp1 and R1 connected in parallel between the input terminal Vin and GND], and between the second input and output terminal and the reference potential connection terminal, respectively [Fig. 7B, Cp2 and R2 connected parallel between the output terminal Vout and GND].
Regarding claim 12, Wang discloses that the wiring pattern of the internal signal line has a symmetrical shape with a surge absorption element as a reference [Fig. 7B, the surge absorption element diode D3 is connected at a midpoint of the internal signal line, which shows a symmetrical shape with diode D3 as a reference].
Regarding claim 13, Wang discloses that the first input and output terminal and the second input and output terminal are disposed at symmetrical positions with the reference potential connection terminal as a reference [Fig. 7B, Vin and Vout terminals are disposed at symmetrical positions with the GND terminal as a reference].
Regarding claim 15, Wang discloses that the transient voltage absorption element [Fig. 7B, Zener diode D3] is configured to connect to a shunt between the signal line and the reference potential [Zener diode D3 functions as a shunt creating an impedance path that divers the damaging current to ground; par. 0054, par. 0055, par. 0057].
Regarding claim 20, Wang discloses that the parasitic capacitance component is generated between the internal signal line and at least one of the first input and output terminal and the second input and output terminal [Fig 7B, Cp1 is generated between Vin and D3, and Cp2 is generated between D3 and Vout], the base material further includes a dielectric layer, and the internal signal line is disposed at a position that faces at least one of the first input and output terminal and the second input and output terminal with the dielectric layer interposed therebetween [Fig. 7B is formed on a printed circuit board, and PCB inherently has a substrate portion which is non-conductive dielectric material that provides mechanical support and electrical insulation between the conductive parts], and the internal signal line is disposed at a position that faces at least one of the first input and output terminal and the second input and output terminal with the dielectric layer interposed therebetween [as shown].
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 9: The prior art does not disclose that the base material further includes two or more layers of the internal signal lines disposed at positions with a dielectric film interposed therebetween. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838