DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant election without traverse Species I-4 shown in Figs. 64-88 in the RESPONSE to Restriction Requirements filed 09/01/26 has been acknowledged.
Applicant stated that all device Claims 1-14 are read on the elected species.
Status of Application and Status of Claims
Current application is a CIP of application 18362743 filed 07/31/23 having a provisional application 63/492,573 filed 03/28/23, has no Figs. 64-88 (chosen by the Applicant for examination) and having no Schottky Barrier Contact (as the current application does). However, the “parent” application has a source contact layer comprising a stack of a barrier layer and a metal layer that are similar the Schottky Barrier Source contact of the current application (though earlier, source metal contact layers did not include aluminum). Accordingly, appropriate prior arts for a claimed (“shaped”) structure (of Figs. 64-88) of the current application are those that are filed (or published, depending on an assignee) earlier that the filing (published) date of the current application - 04/02/24, while for a source contact stack comprised a barrier layer and a metal layer, including a cylindrical portion of the barrier layer disposed inside a memory opening (shown in Fig. 59 of the current application) – appropriate prior arts are those that are filed (or published, depending on an assignee) – earlier than 03/28/23.
Claims 15-20 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-14 are examined on merits herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2022/0130853) in view of Rabkin et al. (US 2017/0110470).
In re Claim 1, Sharangpani teaches a semiconductor structure comprising (Figs. 22A, 22B):
an alternating stack of insulating layers 32 (paragraph 0049) and electrically conductive layers 46 (paragraph 0102) located over a source layer – comprised semiconductor 10 (paragraph 0047) and metallic parts 33/31 (paragraphs 0087, 0115);
a memory opening 49 vertically extending through the alternating stack (opening 49 is shown in Fig. 4A, paragraph 0066; within the opening – there is a memory opening fill structure 55 shown in Fig. 22B, paragraphs 0034, 0083); and
a memory opening fill structure 55 located in the memory opening 49 and comprising
a memory film 50 (paragraph 0082),
a vertical semiconductor channel 60 (paragraph 0082) laterally surrounded by the memory film 50 and in contact with the source layer 10/33/31 (e.g., in contact with 31, paragraph 0087), and
a dielectric core 62 (paragraphs 0079, 0081, where 62 is made from silicon oxide) laterally surrounded by the semiconductor channel 60.
Sharangpani does not teach a dielectric metal oxide liner laterally surrounded by the vertical semiconductor channel, wherein the dielectric core is laterally surrounded by the dielectric metal oxide liner.
Rabkin teaches (Fig. 3F) a dielectric metal oxide liner 622 (made from aluminum oxide, paragraph 0106) laterally (and on the bottom) surrounded by a vertical semiconductor channel 60 (paragraph 0096), wherein the dielectric metal oxide liner 622 laterally surrounds a dielectric core 62 (paragraph 0099, core 62 is made from silicon oxide).
Sharangpani and Rabkin teach analogous arts directed to three-dimensional (3D) NAND memory devices with vertical channels and comprised a dielectric score made from silicon oxide, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sharangpani structure in view of the Rabkin structure, since they are from the same field of endeavor, and Rabkin created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sharangpany device by substituting silicon oxide dielectric core within memory openings with silicon oxide dielectric core covered on sides and bottom with aluminum oxide liner (per Rabkin), creating by that the aluminum oxide liner laterally surrounded by the vertical semiconductor channel and surrounding the dielectric core of silicon oxide, as is shown in Annotated Modified Fig. 22B (where the dielectric metal oxide liner is shown as DMOL) if such dielectric core material is preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Annotated Modified Fig. 22B
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In re Claim 2, Sharangpani/Rabkin teaches the semiconductor structure of Claim 1 as cited above.
Sharangpani/Rabkin further teaches (Sharangpani, Fig. 22B, paragraph 0115) that the source layer 10/33/31 comprises a metallic source layer 33 that includes
a metallic barrier liner 33A comprising conductive metallic nitride material (such as TiN, TaN, and WN), and
a metal layer 33B located on the metallic barrier liner and comprising a metal (such as copper) having (inherently; see at least the current application for support of inherency) - a higher electrical conductivity than the conductive metallic nitride material.
In Claim 3, Sharangpani/Rabkin teaches the semiconductor structure of Claim 1 as cited above, wherein (Annotated Modified Fig. 22B) the source layer 10/33/31 is in contact with an end surface of the dielectric metal oxide liner DMOL (that directly contacts 31).
In re Claim 4, Sharangpani/Rabkin teaches the semiconductor structure of Claim 3 as cited above, wherein (Annotated Modified Fig. 22B) the source layer 10/33/31 is in direct contact with an end surface of the dielectric core 62 (that contacts 31).
In re Claim 5, Sharangpani/Rabkin teaches the semiconductor structure of Claim 3, wherein (Annotated Modified Fig. 22B) a contact area between the dielectric metal oxide liner DMOL and the source layer 10/33/31 has an annular shape – due to annular shape of each of memory openings 49 (see Fig. 4B of Sharangpani) in which the DMOL is disposed.
In re Claim 11, Sharangpani/Rabkin teaches the semiconductor structure of Claim 1 as cited above, wherein, as shown for Claim 1, the dielectric core comprises a silicon oxide core.
In re Claim 12, Sharangpani/Rabkin teaches the semiconductor structure of Claim 1 as cited above, wherein (Annotated Modified Fig. 22B) a top end of the dielectric metal oxide liner DMOL is in contact with a drain region 63 (paragraph 0082) that contacts a top end of the vertical semiconductor channel 60.
Allowable Subject Matter
Claims 6, 7, 8, 13, and 14 contain allowable subject matter, and Claims 9-10 depend on Claim 8. All these claims are objected by the current Office Action since they depend on the rejected base Claim 1. The claims would be allowed to incorporate all limitations of the base claim and all intervening claims.
Reason for Indicating Allowable Subject Matter
Re Claim 6: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 6 as: “an entirety of a contact area between the source layer and the dielectric metal oxide liner is located above a horizontal plane including an interface between the source layer and a bottommost insulating layer within the alternating stack”, in combination with all limitations of Claims 1 and 3, on which Claim 6 depends..
Re Claim 7: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 7 as: “a cylindrical surface of the source layer is in contact with a cylindrical surface segment of an inner sidewall of the vertical semiconductor channel”, in combination with all limitations of Claims 1 and 3, on which Claim 7 depends.
Re Claim 8: The prior arts of record, alone or in combination fail(s) to anticipate or render obvious such limitation of Claim 8 as: “a semiconductor source layer contacting... a cylindrical surface segment of an outer sidewall of the vertical semiconductor channel”, in combination with other limitations of Claim 8 and with all limitations of Claim 1, on which Claim 8 depends.
Re Claim 13: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 13 as: “a top end of the dielectric metal oxide liner is vertically spaced from a drain region” in combination with other limitations of Claim 13 and in combination with all limitations of Claim 1, on which Claim 13 depends.
Re Claim 14: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation as: “a semiconductor oxide layer located between the dielectric metal oxide liner and the vertical semiconductor channel”, in combination with all limitations of Claim 1, on which Claim 14 depends.
The prior arts of record, in addition to Sharangpani et al. (US 2022/0130853) and Rabkin et al. (US 2017/0110470) cited above, also include: Rabkin et al. (US 2017/0110464), Tsutsumi et al. (US 2022/0216145), Yada (US 2024/0332180), Kai et al. (US 2020/0258904), and Rabkin et al. (US 9721963),
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 09/09/26
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