DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 1, 2026 has been entered.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Response to Amendment
The amendment filed May 1, 2026 has been entered. Claims 1, 4-8, 11-15, and 18-20 remain pending in this application. Claims 2-3, 9-10, and 16-17 previously cancelled at applicant’s request. Claims 1, 6-8, 13-15, and 20 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 8, 11-12, 15, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0044746 A1 to Fu-Chang Hsu (hereafter Hsu) in view of US 2019/0227743 A1 to Marc Hamilton (hereafter Hamilton).
Regarding Independent Claim 1, Hsu discloses a memory device comprising:
a memory array comprising a set of memory cells (An array of memory cells: Hsu, ¶[0173]); and
control logic (Control signals: Hsu, ¶[0189]),
operatively coupled with the memory array (Control signals coupled with the memory array: Hsu, ¶[0189] and Figure 2B),
to perform operations comprising:
initiating a program operation to program the set of memory cells (Programming a set of memory cells: Hsu, ¶[0204])
associated with a set of pages comprising
a lower page, an upper page, an extra page, and a top page of the memory device (Using the program operation to program a QLC memory cell: Hsu, ¶[0209]; A set of data pages including lower, upper, extra, and top pages is inherent in programming a QLC memory cell);
causing, during the program operation,
programming of first data of the lower page and the upper page into a first subset of memory cells (Programming lower page data to a subset of memory cells: Hsu, ¶[0379]; This paragraph is in reference to a 2-bit (MLC) cell of lower and upper page data. Hsu explicitly explains this same approach may be applied to QLC data, however: Hsu, ¶[0378]; The ‘lower page’ described in ¶[0379] refers to the least significant bits and are therefore equivalent to the lower and upper page data of the instant invention)
connected to a first subset of even-numbered bitlines associated with a target wordline of the memory device (Programming lower page data to odd bit lines: Hsu, ¶[0379]; The designation of even/odd is arbitrary, broadest reasonable interpretation interprets the key element being alternating bitlines);
causing, during the program operation,
programming of second data of the extra page and the top page into a second subset of memory cells (Programming upper page data to a subset of memory cells: Hsu, ¶[0379]; The ‘upper page’ described in ¶[0379] refers to the most significant bits and are therefore equivalent to the extra and top page data of the instant invention)
connected to a second subset of odd-numbered bitlines associated with the target wordline of the memory device (Programming upper page data to even bit lines: Hsu, ¶[0379]).
receiving a first request to execute a first read operation of the lower page (Receiving a request to read selected data pages: Hsu, ¶[0384]); and
executing the first read operation, wherein executing the first read operation comprises:
causing application of a voltage to the target wordline (Applying a first read voltage: Hsu, ¶[0384]) and
accessing one or more of the even-numbered bitlines (Applying a voltage to the even bit lines: Hsu, ¶[0384]; While shielding via the odd bitlines: Hsu, ¶[0311]); and
causing an output of first data
corresponding to bit positions of the lower page (The data read corresponding to the first subset of data: Hsu, ¶[0384])
following completion of the application of the voltage (Outputting the first subset of data following a read of the even bit lines: Hsu, ¶[0384]).
Hsu fails to disclose the first read operation comprising the application of a single ramping voltage to cause the output of all bit positions following the completion of the single ramping voltage, instead opting for multiple operations at different voltages to read multiple-bit data (Hsu, ¶[0557]). Hamilton, however, discloses a single word line ramp read operation, retrieving data for different bitlines and different data in a single operation (Hamilton, ¶[0017]). Hamilton teaches this ramping read method may take longer than a single discrete read operation, but less cumulative time than would be required for multiple discrete read operations (Hamilton, ¶[0018]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient ramping read operation of Hamilton in the divided programming architecture of Hsu, with a reasonable expectation of success. Both inventions are well known in the field of memory read operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 4 and the substantially similar limitations of Claims 11 and 18, Hsu discloses the memory device of claim 1, the operations further comprising
receiving a second request to execute a second read operation of one of a selected extra page or a selected top page (Receiving a second request to read selected data pages: Hsu, ¶[0385]).
Regarding Claim 5 and the substantially similar limitations of Claims 12 and 19, Hsu discloses the memory device of claim 4, the operations further comprising
executing the second read operation, wherein executing the read operation comprises:
causing application of a second ramping voltage (Disclosing a single ramping voltage on a read operation: Hamilton, ¶[0017]) to the target wordline and accessing one or more of the odd-numbered bitlines (Applying a ramping voltage to the odd bit lines: Hsu, ¶[0385]; While shielding via the even bitlines: Hsu, ¶[0311]); and
causing an output of second data corresponding to all bit positions (Outputting the results of all bit positions during the single ramping voltage: Hamilton, ¶[0017]) of one of the selected extra page or the selected top page following completion of the application of the second ramping voltage (Outputting the upper page stored data following the application of the second read voltage: Hsu, ¶[0385]).
Regarding Independent Claim 8, Hsu discloses a method comprising:
initiating, by a processing device (Disclosing an apparatus: Hsu, ¶[0464]),
a program operation to program a set of memory cells (Programming a set of memory cells: Hsu, ¶[0204])
associated with a set of pages comprising a lower page, an upper page, an extra page, and a top page of a memory device (Using the program operation to program a QLC memory cell: Hsu, ¶[0209]; A set of data pages including lower, upper, extra, and top pages is inherent in programming a QLC memory cell);
causing, during the program operation,
programming of first data of the lower page and the upper page into a first subset of memory cells (Programming lower page data to a subset of memory cells: Hsu, ¶[0379]; This paragraph is in reference to a 2-bit (MLC) cell of lower and upper page data. Hsu explicitly explains this same approach may be applied to QLC data, however: Hsu, ¶[0378]; The ‘lower page’ described in ¶[0379] refers to the least significant bits and are therefore equivalent to the lower and upper page data of the instant invention)connected to a first subset of even-numbered bitlines associated with a target wordline of the memory device (Programming lower page data to odd bit lines: Hsu, ¶[0379]; The designation of even/odd is arbitrary, broadest reasonable interpretation interprets the key element being alternating bitlines);
causing, during the program operation,
programming of second data of the extra page and the top page into a second subset of memory cells (Programming upper page data to a subset of memory cells: Hsu, ¶[0379]; The ‘upper page’ described in ¶[0379] refers to the most significant bits and are therefore equivalent to the extra and top page data of the instant invention)
connected to a second subset of odd-numbered bitlines associated with the target wordline of the memory device (Programming upper page data to even bit lines: Hsu, ¶[0379]),
receiving a first request to execute a first read operation of the lower page (Receiving a request to read selected data pages: Hsu, ¶[0384]); and
executing the first read operation, wherein executing the first read operation comprises:
causing application of a voltage to the target wordline (Applying a first read voltage: Hsu, ¶[0384]) and
accessing one or more of the even-numbered bitlines (Applying a voltage to the even bit lines: Hsu, ¶[0384]; While shielding via the odd bitlines: Hsu, ¶[0311]); and
causing an output of first data
corresponding to bit positions of the lower page (The data read corresponding to the first subset of data: Hsu, ¶[0384])
following completion of the application of the voltage (Outputting the first subset of data following a read of the even bit lines: Hsu, ¶[0384]).
Hsu fails to disclose the first read operation comprising the application of a single ramping voltage to cause the output of all bit positions following the completion of the single ramping voltage, instead opting for multiple operations at different voltages to read multiple-bit data (Hsu, ¶[0557]). Hamilton, however, discloses a single word line ramp read operation, retrieving data for different bitlines and different data in a single operation (Hamilton, ¶[0017]). Hamilton teaches this ramping read method may take longer than a single discrete read operation, but less cumulative time than would be required for multiple discrete read operations (Hamilton, ¶[0018]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient ramping read operation of Hamilton in the divided programming architecture of Hsu, with a reasonable expectation of success. Both inventions are well known in the field of memory read operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 15, Hsu discloses a non-transitory computer-readable storage medium comprising
instructions (Disclosing instructions: Hsu, ¶[0464]) that,
when executed by a processing device (Disclosing an apparatus: Hsu, ¶[0464]),
cause the processing device to perform operations comprising:
initiating a program operation to program a set of memory cells (Programming a set of memory cells: Hsu, ¶[0204])
associated with a set of pages
comprising a lower page, an upper page, an extra page, and a top page of a memory device (Using the program operation to program a QLC memory cell: Hsu, ¶[0209]; A set of data pages including lower, upper, extra, and top pages is inherent in programming a QLC memory cell);
causing, during the program operation,
programming of first data of the lower page and the upper page into a first subset of memory cells (Programming lower page data to a subset of memory cells: Hsu, ¶[0379]; This paragraph is in reference to a 2-bit (MLC) cell of lower and upper page data. Hsu explicitly explains this same approach may be applied to QLC data, however: Hsu, ¶[0378]; The ‘lower page’ described in ¶[0379] refers to the least significant bits and are therefore equivalent to the lower and upper page data of the instant invention)
connected to a first subset of even-numbered bitlines associated with a target wordline of the memory device (Programming lower page data to odd bit lines: Hsu, ¶[0379]; The designation of even/odd is arbitrary, broadest reasonable interpretation interprets the key element being alternating bitlines);
causing, during the program operation,
programming of second data of the extra page and the top page into a second subset of memory cells (Programming upper page data to a subset of memory cells: Hsu, ¶[0379]; The ‘upper page’ described in ¶[0379] refers to the most significant bits and are therefore equivalent to the extra and top page data of the instant invention)
connected to a second subset of odd-numbered bitlines associated with the target wordline of the memory device (Programming upper page data to even bit lines: Hsu, ¶[0379]),
receiving a first request to execute a first read operation of the lower page (Receiving a request to read selected data pages: Hsu, ¶[0384]); and
executing the first read operation, wherein executing the first read operation comprises:
causing application of a voltage to the target wordline (Applying a first read voltage: Hsu, ¶[0384]) and
accessing one or more of the even-numbered bitlines (Applying a voltage to the even bit lines: Hsu, ¶[0384]; While shielding via the odd bitlines: Hsu, ¶[0311]); and
causing an output of first data
corresponding to bit positions of the lower page (The data read corresponding to the first subset of data: Hsu, ¶[0384])
following completion of the application of the voltage (Outputting the first subset of data following a read of the even bit lines: Hsu, ¶[0384]).
Hsu fails to disclose the first read operation comprising the application of a single ramping voltage to cause the output of all bit positions following the completion of the single ramping voltage, instead opting for multiple operations at different voltages to read multiple-bit data (Hsu, ¶[0557]). Hamilton, however, discloses a single word line ramp read operation, retrieving data for different bitlines and different data in a single operation (Hamilton, ¶[0017]). Hamilton teaches this ramping read method may take longer than a single discrete read operation, but less cumulative time than would be required for multiple discrete read operations (Hamilton, ¶[0018]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient ramping read operation of Hamilton in the divided programming architecture of Hsu, with a reasonable expectation of success. Both inventions are well known in the field of memory read operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 6-7, 13-14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0044746 A1 to Fu-Chang Hsu (hereafter Hsu) and US 2019/0227743 A1 to Marc Hamilton (hereafter Hamilton) further in view of US 11,960,758 B2 to Bhanushankar Doni Gurudath, et al. (hereafter Gurudath).
Regarding Claim 6 and the substantially similar limitations of Claims 13, Hsu discloses the memory device of claim 1, but fails to expressly disclose the further limitations of Claim 6. Gurudath, however, discloses a memory array as in Claim 1, wherein
the first subset of memory cells comprises a first memory cell comprising a first bit position and a second bit position storing data associated with the lower page (Storing Lower and Middle page data: Gurudath, Figure 6B).
Gurudath discloses this division of data can improve performance (Gurudath, col.7:1-3). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient programming structure of Gurudath with the divided programming architecture of Hsu, with a reasonable expectation of success. Both inventions are well known in the field of QLC programming and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 7 and the substantially similar limitations of Claims 14, Gurudath discloses the memory device of claim 6, wherein the first memory cell comprises
a third bit position and a fourth bit position storing data associated with the upper page (Storing Upper and Top page data: Gurudath, Figure 6B).
Regarding Claim 20, Hsu discloses the non-transitory computer-readable storage medium of claim 15, but fails to disclose the further limitations of Claim 20. Gurudath, however, discloses a storage medium as in Claim 15, wherein
the first subset of memory cells comprises a first memory cell comprising a first bit position and a second bit position storing data associated with the lower page (Storing Lower and Middle page data: Gurudath, Figure 6B); and
wherein the first memory cell comprises a third bit position and a fourth bit position storing data associated with the upper page (Storing Upper and Top page data: Gurudath, Figure 6B).
Gurudath discloses this division of data can improve performance (Gurudath, col.7:1-3). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient programming structure of Gurudath with the divided programming architecture of Hsu, with a reasonable expectation of success. Both inventions are well known in the field of QLC programming and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220415389 A1 to Violante Moshiano, et al.: Disclosing staged programming of QLC memory cells.
US 8369156 B2 to Yan Li: Disclosing inhibiting alternating bitlines during reading to speed up reading operations.
US 8179727 B2 to Hyung-Gon Kim: Disclosing separating TLC data into separate pages for programming to separate memory cells.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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