DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The disclosure is objected to because of the following informalities: on page 11 of the spec, dated 4/2/2024, paragraph number sequencing needs to be corrected, [0041] is followed by [0024], and this leads to many duplicated numberings of paragraphs.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-11, 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Papandreou et al. (PGPUB 20210065813), hereinafter as Papandreou, in view of Papandreou et al. (PGPUB 20210134377), hereinafter as P2.
Regarding claim 1, Papandreou teaches a memory system comprising:
a memory component comprising a plurality of pages (Fig 5, MLC is known with upper, lower pages, at least [0077]); and
a processing device programmed to perform operations comprising:
issuing a first block family error avoidance (BFEA) scan on a lower page of the memory component to determine a lower page bin (Fig 6, step 604-606 calibration is well known in the field to comprise a read/scan action, and [0082] e.g. lower/upper pages use a set of offsets (/bins) of the same group);
issuing a second BFEA scan on an upper page of the memory component to determine an upper page bin (Fig 6, and [0082] e.g. lower/upper pages use a set of offsets of the same group); and
issuing a third BFEA scan on an extra page of the memory component to determine an extra page bin ([0081] it is known that a TLC memory has three pages),
but not expressly checking a raw bit error rate of the lower page of the memory component at multiple voltage offsets against a predetermined threshold,
P2 teaches checking a raw bit error rate of the lower page of the memory component at multiple voltage offsets against a predetermined threshold (Fig 6A, step 606-622-612).
Since Papandreou and P2 are both from the same field of memory device, the purpose disclosed by P2 would have been recognized in the pertinent art of Papandreou.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use an error limit/range as in P2 into the device of Papandreou for the purpose of get proper reading voltages for the memory device.
Regarding claim 2, Papandreou teaches storing data representing the lower page bin, the upper page bin, and the extra page bin in static random-access memory (SRAM) ([0115] stored in a memory, it is well known SRAM is possible for such memory).
Regarding claim 3, Papandreou teaches in response to a read request from a host (Fig 1, 201): accessing the SRAM to determine the lower page bin, the upper page bin, and the extra page bin; determining a lower page read offset voltage based on the lower page bin; determining an upper page read offset voltage based on the upper page bin; determining an extra page read offset voltage based on the extra page bin; modifying a lower page read voltage using the lower page read voltage offset to generate a modified lower page read voltage; modifying an upper page read voltage using the upper page read voltage offset to generate a modified upper page read voltage; modifying an extra page read voltage using the extra page read voltage offset to generate a modified extra page read voltage; using the modified page read voltages to read lower page data, upper page data, and extra page data from the memory component (Fig 6-8, and at least [0081-82]); and providing the read lower page data, the upper page data, and the extra page data to the host (Fig 1).
Regarding claim 4, Papandreou teaches periodically repeating the first BFEA scan, the second BFEA scan, and the third BFEA scan ([0089]).
Regarding claim 8, Papandreou teaches a method comprising:
issuing, by a processing device, a first block family error avoidance (BFEA) scan on a lower page of a memory component comprising a plurality of memory cells to determine a lower page bin (Fig 6, step 604-606 and [0082]);
issuing, by the processing device, a second BFEA scan on an upper page of the memory component to determine an upper page bin (Fig 6, step 604-606 and [0082]); and
issuing, by the processing device, a third BFEA scan on an extra page of the memory component to determine an extra page bin ([0081] it is known that a TLC memory has three pages),
P2 teaches checking a raw bit error rate of the lower page of the memory component at multiple voltage offsets against a predetermined threshold (Fig 6A, step 606-622-612).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 9, argument used in rejection of claim 2 applies.
Regarding claim 10, argument used in rejection of claim 3 applies.
Regarding claim 11, argument used in rejection of claim 4 applies.
Regarding claim 15, Papandreou teaches a non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
issuing a first block family error avoidance (BFEA) scan on a lower page of a memory component comprising a plurality of memory cells to determine a lower page bin;
issuing a second BFEA scan on an upper page of the memory component to determine an upper page bin; and
issuing a third BFEA scan on an extra page of the memory component to determine an extra page bin (argument used in rejection of claim 1 applies);
P2 teaches checking a raw bit error rate of the lower page of the memory component at multiple voltage offsets against a predetermined threshold (Fig 6A, step 606-622-612).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 16, argument used in rejection of claim 2 applies.
Regarding claim 17, argument used in rejection of claim 3 applies.
Regarding claim 18, argument used in rejection of claim 4 applies.
Claim(s) 5-7, 12-14, 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Papandreou and P2, in view of Shirakawa et al. (PGPUB 20220093199), hereinafter as Shirakawa.
Regarding claim 5, Papandreou and P2 teach a system as in rejection of claim 1,
But not expressly the first BFEA scan of the lower page of the memory component scans at R1 and R5 of triple-level cell (TLC) memory cells,
Shirakawa teaches the first BFEA scan of the lower page of the memory component scans at R1 and R5 of triple-level cell (TLC) memory cells (Fig 14).
Since Shirakawa and Papandreou are both from the same field of semiconductor memory device, the purpose disclosed by Shirakawa would have been recognized in the pertinent art of Papandreou.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use read voltages as in Shirakawa into the device of Papandreou for the purpose of reading data out of memory cells.
Regarding claim 6, Shirakawa teaches the second BFEA scan of the upper page of the memory component scans at R2, R4, and R6 of triple-level cell (TLC) memory cells (Fig 14).
The reason for combining the references used in rejection of claim 5 applies.
Regarding claim 7, Shirakawa teaches the third BFEA scan of the extra page of the memory component scans at R3 and R7 of triple-level cell (TLC) memory cells (Fig 14).
The reason for combining the references used in rejection of claim 5 applies.
Regarding claim 12, argument used in rejection of claim 5 applies.
Regarding claim 13, argument used in rejection of claim 6 applies.
Regarding claim 14, argument used in rejection of claim 7 applies.
Regarding claim 19, argument used in rejection of claim 5 applies.
Regarding claim 20, argument used in rejection of claim 6 applies.
Regarding claim 21, argument used in rejection of claim 7 applies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827