DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse to the species of Group I Figs. 6a-17b in the reply filed on 06/29/2026.
Claims 1-8 and 20 will be withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species of Group II, there being no allowable generic or linking claim.
Since Claim 1 states “wherein a bottom portion of the source/drain region extends into a backside interlevel dielectric layer” and since Claim 20 states “wherein a top surface of the backside contact is below a bottom surface of the first gate structure and a bottom surface of the second gate structure.” Both claim 1 and Claim 20 are determined to pertain to the species of Group II and thus their dependents also pertain to Group II
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9-13 and 15-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sangmoon Lee (US 20240266256 A1) hereinafter referred to as “Lee”.
Regarding Claim 9 Lee teaches
A semiconductor structure (Fig 5a), comprising:
a plurality of nanosheet channel layers (CH1 comprising the plurality SP1-SP3), wherein the plurality of nanosheet channel layers (CH1 (and/or one of the identical adjacent structures)) define a channel region;
a gate structure (GE) on the channel region;
a source/drain liner layer (BFL fig 5a) disposed of sidewalls of the plurality of nanosheet channel layers and the gate structure; (BFL is disposed on GE and on the sidewalls of CH1 Fig 5a)
a source/drain region (MAL of SD1(and/or one of the identical adjacent structures)) disposed on the source/drain liner layer (BFL); and
a backside contact (BSC1 (and/or one of the identical adjacent structures)Para [0085]) connected to a bottom portion of the source/drain region(Para [0085]); wherein the bottom portion of the source/drain region (bottom of MAL) is isolated from the gate structure (GE) by the source/drain liner layer (BFL) and a protecting liner layer(GI) arranged between the gate structure (GE) and the source/drain liner layer.(BFL)(GI Is between GE and BFL)
Regarding Claim 10 Lee teaches
The semiconductor structure according to claim 9,
wherein a bottom portion of the gate structure (PO1) has tapered sides. (Fig 5a Para [0055])
Regarding Claim 11 Lee teaches
The semiconductor structure according to claim 9,
wherein a bottom portion of the gate structure (PO1) has a trapezoid configuration. (Fig 5a Para [0055])
Regarding Claim 12 Lee teaches
The semiconductor structure according to claim 9,
wherein a top surface of the backside contact (BSC) is above a bottom surface of the gate structure. (Para [0090][0050][0053][0103][0126] teaches the reasons for the shape of MAL and BSC and in light of the figures 5a Lee teaches this limitation)
Regarding Claims 13 Lee teaches
The semiconductor structure according to claim 9,
wherein the plurality of nanosheet channel layers (CH1) comprises a top-most nanosheet channel layer (SP3) and a bottom-most nanosheet channel layer (SP1), and wherein a top surface (surface of GI on top of PO1) of the protecting liner layer (GI) is below a bottom surface of the bottom-most nanosheet channel layer. (bottom surface of SP1 Fig 5a)
Regarding Claim 15 Lee teaches
The semiconductor structure according to claim 9,
wherein the source/drain liner layer (BFL) comprises silicon. (Para [0050] teaches silicon)
Regarding Claim 16 Lee teaches
The semiconductor structure according to claim 9,
wherein the protecting liner layer (GI) comprises a nitride material. (Para [0066])
Regarding claim 17 Lee teaches
The semiconductor structure according to claim 9,
wherein the protecting liner layer (GI) is further arranged between the bottom portion of the gate structure (GE) and backside contact (BSC). (GI is between GE and BSC)
Regarding Claim 18 Lee teaches
A semiconductor structure (Fig 5a), comprising:
a first nanosheet device (see diagram of fig 5a below) comprising:
a first gate structure (GE) on a first channel region (see diagram below); and
a first source/drain liner layer (BFL see diagram below) disposed on sidewalls of the first gate structure;
a second nanosheet device (see diagram below) adjacent the first nanosheet device, the second nanosheet device comprising:
a second gate structure (GE see diagram below) on a second channel region; and
a second source/drain liner layer (BFL see diagram below) disposed on sidewalls of the second gate structure;
a source/drain region (MAL see diagram below) disposed between opposing sidewalls of the first source/drain liner layer and the second source/drain liner layer; and
a backside contact (BSC see diagram below) connected to a bottom portion of the source/drain region(MAL); wherein the bottom portion of the source/drain region is isolated from the first gate structure by the first source/drain liner layer and a first protecting liner layer (GI on the first gate structures) arranged between the first gate structure and the first source/drain liner layer(see diagram below); and
wherein the bottom portion of the source/drain region is isolated from the second gate structure by the second source/drain liner layer and a second protecting liner layer (GI on the second gate structures) arranged between the second gate structure and the second source/drain liner layer. (see diagram below)
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Regarding Claim 19 Lee teaches
The semiconductor structure according to claim 18,
wherein a bottom portion of the first gate structure and a bottom portion of the second gate structure each have a trapezoid configuration. (Fig 5a Para [0055])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 13 above, and further in view of Li-Zhen Yu (US 11710664 B2) Hereinafter referred to as “Yu”.
Regarding Claim 14 Lee teaches
The semiconductor structure according to claim 13,
Lee is not relied upon to teach
wherein a bottom surface of the source/drain region is above the bottom surface of the bottom-most nanosheet channel layer.
Yu teaches a similar source drain region connection process and is relied upon to teach
wherein a bottom surface of the source/drain region (Fig 6 (A1) element108) is above the bottom surface of the bottom-most nanosheet channel layer (154). (Fig 6(A1) Col 13 lines 22-60)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lee such that the device uses the source/drain connection process described in Yu that would result in the source/drain being above the lowermost channel layer because the modification allows for the reduction of routing resistance and contact resistance while it enlarges alignment. (Col 16 lines 9-22, Col 13 lines 22-60)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang; Tsung-Sheng (US-12720853-B2), NA; Sangcheol (US-20260013180-A1), Hong; Wonhyuk (US-12255248-B2), KIM; Gyeom (US-20240282830-A1), Xie; Ruilong (US-20240113176-A1), Li; Tao (US-20240113193-A1), LEE; Jongjin (US-20240105615-A1), SHEN; Shu-Wen (US-20240088223-A1)
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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