Prosecution Insights
Last updated: July 17, 2026
Application No. 18/624,788

METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT BY USING ATOMIC LAYER ETCHING (ALE) PROCESS

Non-Final OA §102
Filed
Apr 02, 2024
Priority
May 15, 2023 — RE 10-2023-0062692
Examiner
CULBERT, ROBERTS P
Art Unit
1716
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
666 granted / 816 resolved
+16.6% vs TC avg
Minimal -4% lift
Without
With
+-3.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
839
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
63.6%
+23.6% vs TC avg
§102
14.8%
-25.2% vs TC avg
§112
3.5%
-36.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 816 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 7, 9, 13, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2017/0186621 to Zaitsu. Regarding Claim 1, Zaitsu teaches a method of manufacturing a semiconductor element, the method comprising: placing a structure, the structure comprising a substrate and a first metal-containing film (Paragraph 33) disposed on the substrate; fluorinating at least one atomic layer from an exposed surface of the first metal-containing film by supplying a fluorinating gas to the structure to form a fluorinated atomic layer (Paragraph 30); and etching the fluorinated atomic layer of the first metal-containing film by supplying an etching gas to the structure, wherein the etching gas comprises an inert gas in a plasma state (Paragraph 32). Regarding Claim 2, Zaitsu teaches (Paragraph 30) the fluorinating gas comprises a fluorocarbon gas. Regarding Claim 3, Zaitsu teaches (Paragraph 30) the fluorinating gas comprises trifluoromethane (CHF₃) or octafluorocyclobutane (C₄F₈). Regarding Claim 4, Zaitsu teaches (Paragraph 30) supplying trifluoromethane (CHF₃) or octafluorocyclobutane (C₄F₈) wherin etching is performed for an amount of time (implicit) Regarding Claim 5, Zaitsu teaches (Paragraph 35) after the fluorinating and the etching, supplying a purge gas to the structure. Regarding Claim 7, Zaitsu teaches (Paragraph 33) the first metal-containing film comprises at least one of aluminum (Al), zirconium (Zr), iron (Fe), manganese (Mn), magnesium (Mg), chromium (Cr), silicon (Si), gallium (Ga), zinc (Zn), lead (Pb), germanium (Ge), tin (Sn), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), cobalt (Co), niobium (Nb), hafnium (Hf), nickel (Ni), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), palladium (Pd), silicon-germanium (SiGe), silicon nitride (Si₃N₄), titanium oxide (TiO₂), SiOCH, hafnium silicon oxynitride (HfSiON), hafnium silicon oxide (HfSiOx), lanthanum aluminum oxide (LaAlOx), lanthanum oxide (La₂O₃), lanthanum silicon oxide (LaSiOx), zirconium oxide (ZrO₂), tantalum nitride (TaN), titanium nitride (TiN), aluminum oxide (Al₂O₃), and hafnium oxide (HfO₂) (x is a natural number). Regarding Claim 9, Zaitsu teaches (ALE cycles) the fluorinating and the etching are repeated until a thickness of the first metal-containing film reaches a preset target thickness (See at least Paragraphs 8, 20, 39, 42). Regarding Claim 13, Zaitsu teaches a method of manufacturing a semiconductor element, the method comprising: placing a sample in a process chamber (3) of an etching device (Fig 1A), the sample comprising a substrate (1) and a metal-containing film disposed on the substrate (Paragraph 33); performing a first fluorination process by injecting a first fluorinating gas into the process chamber (Paragraph 30); performing a first etching process by injecting a first etching gas into the process chamber (Paragraph 32); performing a second fluorination process (Paragraph 39) by injecting a second fluorinating gas into the process chamber (multiple cycles); and performing a second etching process (second cycle) by injecting a second etching gas into the process chamber, wherein the first etching gas and the second etching gas each comprise an inert gas in a plasma state (Paragraph 32). Regarding Claim 19, Zaitsu teaches method of manufacturing a semiconductor element, the method comprising: placing a sample in a process chamber (3) tof an etching device (Fig 1A), the sample comprising a substrate (1), an element structure disposed on the substrate, and a metal-containing film disposed on the element structure (Figure 5A-5C); performing a first fluorination process by injecting a first fluorination gas into the process chamber(Paragraph 30); supplying a first purge gas to the process chamber (Paragraph 23, 35 and 39); performing a first etching process by injecting a first etching gas into the process chamber (Paragraph 32); supplying a second purge gas to the process chamber; performing a second fluorination process (Paragraph 39) by injecting a second fluorinating gas into the process chamber (multiple cycles); supplying a third purge gas to the process chamber; performing a second etching process by injecting a second etching gas into the process chamber (second cycle); and supplying a fourth purge gas to the process chamber, wherein the first etching gas and the second etching gas each comprise an inert gas in a plasma state (Paragraph 32). Regarding Claim 20, Zaitsu teaches (Paragraph 32) the first purge gas, the first etching gas, and the second purge gas comprise the same material as each other (noble gas), and the third purge gas, the second etching gas, and the fourth purge gas comprise the same material (noble gas), as each other. Allowable Subject Matter Claims 6, 8, 10-12, 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Roberts P Culbert whose telephone number is (571)272-1433. The examiner can normally be reached Monday thru Thursday 7:30 AM-6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Parviz Hassanzadeh can be reached at 571-272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERTS P CULBERT/Primary Examiner, Art Unit 1716
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
May 06, 2026
Non-Final Rejection mailed — §102
Jun 11, 2026
Applicant Interview (Telephonic)
Jun 12, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685058
POLISHING LIQUID AND CHEMICAL MECHANICAL POLISHING METHOD
4y 7m to grant Granted Jul 14, 2026
Patent 12679997
AMINE-BASED COMPOSITIONS FOR USE IN CMP WITH HIGH POLYSILICON RATE
3y 8m to grant Granted Jul 14, 2026
Patent 12677618
COMPOSITION AND METHOD FOR TREATING SUBSTRATE
3y 4m to grant Granted Jul 07, 2026
Patent 12672524
HARD MASK STRESS MODULATION USING LOW ENERGY IMPLANT
2y 0m to grant Granted Jun 30, 2026
Patent 12663567
METHOD FOR FABRICATING A BLAZED GRATING
2y 7m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
78%
With Interview (-3.5%)
2y 4m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 816 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month