CTNF 18/624,825 CTNF 101830 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note by the Examiner For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis. Claim Objections 07-29-01 AIA Claim 12 is objected to because of the following informalities: data is misspelled in “date conductive layer” . Appropriate correction is required. 07-29-01 AIA Claim 25 is objected to because of the following informalities: data is misspelled in “date conductive layer” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 5-12 and 19-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With regards to claim 5 , multiple different voltage lines and a gate line are claimed to be a part of a third gate layer even though they are shown separate of each other in Fig. 9. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 6 , claim 6 is rejected because it is dependent on claim 5. With regards to claim 7 , multiple different voltage lines with a data line are claimed to be a part of a data conductive layer even though they are shown separate of each other in Fig. 11. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 8 , claim 8 is rejected because it is dependent on claim 7. With regards to claim 9 , multiple active pattern layers are claimed to be a part of an active layer even though they are shown separate of each other in Fig. 4. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the active patterns will be treated as separate layers. With regards to claim 10 , multiple gate electrodes are claimed to be a part of a first gate layer even though they are shown separate of each other in Fig. 5. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the gate electrodes will be treated as separate layers. With regards to claim 11 , a gate line and a voltage line are claimed to be part of a third gate layer even though they are shown separate of each other in Fig. 9. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 12 , claim 12 is rejected because it is dependent on claim 11. With regards to claim 19 , multiple different voltage lines and a gate line are claimed to be formed as a same layer even though they are shown separate of each other in Fig. 9. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 20 , claim 20 is rejected because it is dependent on claim 19. With regards to claim 21 , multiple different voltage lines with a data line are claimed to be a part of a data conductive layer even though they are shown separate of each other in Fig. 11. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 22 , claim 22 is rejected because it is dependent on claim 21. With regards to claim 23 , multiple active pattern layers are claimed to be formed as a same layer even though they are shown separate of each other in Fig. 4. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the active patterns will be treated as separate layers. With regards to claim 24 , a gate line and a voltage line are claimed to be formed as a same layer even though they are shown separate of each other in Fig. 9. Because of this separation, each constitute their own layer, which contradicts what is claimed. For examining purposes, the lines will be treated as separate layers. With regards to claim 25 , claim 25 is rejected because it is dependent on claim 24. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-4, 9, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (Pub. No.: US 20220059792 A1), hereinafter as A_Park, in view of Park et al. (Pub. No.: US 20200258970 A1), hereinafter as B_Park . [Livingston (Electronic Properties of Engineering Materials, 1999) is utilized herein as evidence.] With regards to claim 1 , A_Park teaches a display device comprising: an active level (see A_Park Fig. 2, first semiconductor layer A1 and second semiconductor layer A2) disposed on a substrate (see A_Park Fig. 2, substrate 100) ; a first gate level (see A_Park Fig. 2, first gate electrode G1 and second gate electrode G2) disposed on the active level (see A_Park Fig. 2) and including a first gate electrode (see A_Park Fig. 2, first gate electrode G1) ; and a second gate level (see A_Park Fig. 2, top electrode CE2) disposed on the first gate level (see A_Park Fig. 2) and including a capacitor electrode (see A_Park Fig. 2, top electrode CE2) partially overlapping the first gate electrode, the capacitor electrode and the first gate electrode forming a first capacitor (see A_Park Fig. 2, storage capacitor Cst) . A_Park does not teach a third gate level disposed on the second gate level and including a first power voltage line partially overlapping the capacitor electrode and receiving a first power voltage, the first power voltage line and the capacitor electrode forming a second capacitor; a data conductive level disposed on the third gate level ; and an inorganic insulating layer disposed between the third gate level and the data conductive level , and covering the third gate level . B_Park teaches a third gate level (see B_Park Fig. 5, second conductive pattern; and see B_Park [0110]: “The second conductive pattern may include an initializing voltage line IVL and a first power voltage line PVL1.”) disposed on a second gate level (see B_Park Fig. 5, first conductive layer, see B_Park [0099] and [0109]: “The first conductive pattern may include a first gate electrode G1, an (n−1)-th scan line SLn−1, an n-th scan line SLn and an n-th light-emitting line ELn.” “A second conductive layer may be formed on the second insulation layer 130 and may be patterned to form a second conductive pattern.”) and including a first power voltage line (see B_Park Fig. 5, first power voltage line PVL1; see B_Park [0110]: “The second conductive pattern may include an initializing voltage line IVL and a first power voltage line PVL1.”) partially overlapping a capacitor electrode (see B_Park Fig. 5, first gate electrode G1) and receiving a first power voltage (see B_Park [0053]: “The first power voltage lines PVL1 may transfer a first light-emitting power voltage ELVDD provided from the main driver 200 to the pixels P.”) , the first power voltage line and the capacitor electrode forming a second capacitor (see B_Park Fig. 5, first storage capacitor CST1) ; a data conductive level (see B_Park Fig. 5, third conductive layer; and see B_Park [0119]: “Referring to FIGS. 5 and 10, a third conductive layer may be formed on the substrate 110 having the contact holes CH, the first via holes VH1 and the second via holes VH2 and patterned to form a third conductive pattern.”; and Park [0120]: “The third conductive pattern may include an m-th data line DLm, a second power voltage line PVL2, a first electrode pattern EP1, a second electrode pattern EP2 and a third electrode pattern EP3.”) disposed on the third gate level (see B_Park Fig. 5) ; an inorganic insulating layer (see B_Park Fig. 5, third insulation layer 140; and see B_Park [0114]: “The third insulation layer 140 may include an inorganic insulation layer including silicon nitride, silicon oxide, silicon oxynitride or the like, an organic insulation layer including an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin or the like, or combination thereof.”) disposed between the third gate level and the data conductive level , and covering the third gate level (see B_Park Fig. 5) ; and a light emitting element (see B_Park Fig. 5, organic light-emitting diode OLED) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the top layers disposed upon the second gate level of A_Park with the top layers (the third gate level through the light emitting element) taught by B_Park in order to assign the TFTs jobs (by adding a data line, see A_Park [0064]: “The second thin-film transistor T2 may be coupled (e.g., connected) to a data line to serve as a switching thin-film transistor.”) and to increase capacitance by adding an additional capacitor. With regards to claim 2 , the combined device of A_Park and B_Park teaches the display device of claim 1, wherein the inorganic insulating layer (see B_Park Fig. 5, third insulation layer 140) directly contacts the third gate level (see B_Park Fig. 5, first power voltage line PVL1, which is part of the second conductive pattern (see B_Park [0110])) . With regards to claim 3 , the combined device of A_Park and B_Park teaches the display device of claim 1, further comprising: a light emitting element (see B_Park Fig. 5, organic light-emitting diode OLED) disposed on the data conductive level (see B_Park Fig. 5 and B_Park [0119], third conductive layer) and including an anode electrode (see B_Park Fig. 5, first diode electrode E1; see Park [0059]: “The first diode electrode E1 may be an anode, and the second diode electrode E2 may be a cathode.”) ; an organic insulating layer (see B_Park Fig. 5, fourth insulation layer 150; and see B_Park [0127]: “The fourth insulation layer 150 may include an organic insulation layer, which may include an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin or the like, and/or an inorganic insulation layer, which includes silicon nitride, silicon oxide, silicon oxynitride or the like, or a combination thereof.”) disposed between the data conductive level and the anode electrode (see B_Park Fig. 5) ; and a pixel defining layer (see B_ Park Fig. 5, fifth insulation layer 160) disposed on the organic insulating layer and covering an edge portion of the anode electrode (see B_ Park Fig. 5) , wherein any organic insulating layer other than the organic insulating layer is not disposed between the organic insulating layer and the pixel defining layer (see B_Park Fig. 5, where fifth insulation layer 160 is directly on top of fourth insulation layer 150, with no other insulating layer in between. Also, fourth insulation layer 150 may comprise of two layers, one organic and the other inorganic (see B_Park [0127]), with the inorganic layer disposed between the organic layer and fifth insulation layer 160. This structure also teaches the limitation.) . With regards to claim 4 , the combined device of A_Park and B_Park teaches the display device of claim 3, wherein the light emitting element (see B_ Park Fig. 5, organic light-emitting diode OLED) further includes a cathode electrode (see B_ Park Fig. 5, second diode electrode E2; see B_Park [0059]: “The first diode electrode E1 may be an anode, and the second diode electrode E2 may be a cathode.”) disposed on the anode electrode (see B_ Park Fig. 5, first diode electrode E1) , the cathode electrode that receives a second power voltage (see B_Park [0059]: “A second light-emitting power voltage ELVSS may be applied to the second diode electrode E2.”) , and the first power voltage has a higher voltage level than the second power voltage (In applicant’s Fig. 2, the light emitting element LED is electrically written as a diode. Therefore, the anode electrode is associated with the p- side and the cathode electrode is associated with the n-side, especially since the cathode electrode receives the second power voltage ELVSS. In B_Park Fig. 2, organic light-emitting diode OLED is electrically written as a diode, with first diode electrode E1 before the organic light-emitting diode OLED and second diode electrode E2 after it. Therefore, the first diode electrode E1, which is the anode electrode, is associated with the p-side and the second diode electrode E2, which is the cathode electrode, is associated with the n-side. According to page 292 of Livingston, “Current flow is easy when a p-n junction is forward biased (attracting majority carriers to junction) and hard when the junction is reversed biased (attracting minority carriers to junction).” With this, it would have been obvious for a person having ordinary skill in the art to supply the first diode electrode E1 with a higher voltage level than the second diode electrode E2 in order for the organic light-emitting diode OLED to function.) . With regards to claim 9 , the combined device of A_Park and B_Park teaches the display device of claim 1, wherein the active level (see A_Park Fig. 2, first semiconductor layer A1 and second semiconductor layer A2) includes a first active pattern layer (see A_Park Fig. 2, first semiconductor layer A1) and a second active pattern layer (see A_Park Fig. 2, second semiconductor layer A2) spaced apart from each other (see A_Park Fig. 2) , the first gate electrode (see A_Park Fig. 2, first gate electrode G1) partially overlaps the first active pattern layer (see A_Park Fig. 2) , and the first gate electrode and a part of the first active pattern layer form a first transistor (see A_Park Fig. 2, first thin-film transistor T1) . With regards to claim 10 , the combined device of A_Park and B_Park teaches the display device of claim 9, wherein the first gate level (see A_Park Fig. 2, first gate electrode G1 and second gate electrode G2) further includes a second gate electrode (see A_Park Fig. 2, second gate electrode G2) spaced apart from the first gate electrode (see A_Park Fig. 2, first gate electrode G1) and partially overlapping the second active pattern layer (see A_Park Fig. 2, second semiconductor layer A2) , and the second gate electrode and a part of the second active pattern layer form a second transistor (see A_Park Fig. 2, second thin-film transistor T2) . With regards to claim 13 , the combined device of A_Park and B_Park teaches the display device of claim 1, wherein the substrate (see A_Park Fig. 2, substrate 100) includes a glass substrate (see A_Park [0061]: “The substrate 100 may include (e.g., be) glass, metal, and/or a polymer resin.”) . Claims 5, 6, 11, and 12 are rejected under 35 U.S.C. 103 as being obvious over A_Park and B_Park in view of Jeon et al. (Pub. No.: US 20230230964 A1), hereinafter as Jeon, using Jeon’s foreign priority date of Jan. 17, 2022. The applied reference Jeon has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). PNG media_image1.png 768 643 media_image1.png Greyscale Image A: Fig. 10 of Jeon showcasing two individual initialization voltage lines With regards to claim 5 , the combined device of A_Park and B_Park teaches the display device of claim 3. The combined device of A_Park and B_Park does not teach that the third gate level further includes: a first initialization voltage line that receives a first initialization voltage; a second initialization voltage line that receives a second initialization voltage; a first reference voltage line that receives a reference voltage; a gate line that receives a gate signal; and a bias voltage line that receives a bias voltage. Jeon teaches a third gate level (see Jeon Fig. 10, first source metal layer; and see Jeon [0175]: “Referring to FIGS. 6, 10, and 11, the first source metal layer disposed on the second gate metal layer may include initialization voltage lines VIL, a k-th scan initialization line GILk, a k-th scan write line GWLk, a k-th PWM light emitting line PWELk, a first horizontal power line HVDL, a gate-off voltage line VGHL, a k-th sweep signal line SWPLk, a k-th scan control line GCLk, a k-th PAM light emitting line PAELk, a test signal line TSTL, and a third horizontal power line HVSL that extend in the first direction DR1.”) including : a first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) that receives a first power voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) ; a first initialization voltage line (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines as shown in Image A) that receives a first initialization voltage (because the initialization voltage lines are completely separate (as shown in Image A), they would receive two separate initialization voltages.) ; a second initialization voltage line (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines as shown in Image A) that receives a second initialization voltage (because the initialization voltage lines are completely separate (as shown in Image A), they would receive two separate initialization voltages.) ; a first reference voltage line (see Jeon Fig. 10, third horizontal power line HVSL) that receives a reference voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) ; a gate line (see Jeon Fig. 10, k-th scan write line GWLk) that receives a gate signal (see Jeon [0125]: “The second transistor T2 is turned on by a k-th scan write signal of a k-th scan write line GWLk”) ; and a bias voltage line (see Jeon Fig. 10, k-th sweep signal line SWPLk. In applicant’s Fig. 2, bias voltage VBIAS is connected to the source of eighth transistor T8. In Jeon Fig. 5, k-th sweep signal line SWPLk is connected to the source of seventh transistor T7. Because VBIAS and SWPLk are both source lines, they are analogous.) that receives a bias voltage (see Jeon [0110]: “The sweep signal driver 113 may output PWM light emitting signals to the PWM light emitting lines PWEL and output sweep signals to the sweep signal lines SWPL according to the first light emitting control signal.”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the third gate level of A_Park and B_Park with the third gate level taught by Jeon in order to have all the required wiring to drive the circuit while also saving space. With regards to claim 6 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 5, wherein each of the first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) , the gate line (see Jeon Fig. 10, k-th scan write line GWLk) , the first and second initialization voltage lines (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines shown) , the first reference voltage line (see Jeon Fig. 10, third horizontal power line HVSL) , and the bias voltage line (see Jeon Fig. 10, k-th sweep signal line SWPLk) extends in a first direction (see Jeon [0175]: “Referring to FIGS. 6, 10, and 11, the first source metal layer disposed on the second gate metal layer may include initialization voltage lines VIL, a k-th scan initialization line GILk, a k-th scan write line GWLk, a k-th PWM light emitting line PWELk, a first horizontal power line HVDL, a gate-off voltage line VGHL, a k-th sweep signal line SWPLk, a k-th scan control line GCLk, a k-th PAM light emitting line PAELk, a test signal line TSTL, and a third horizontal power line HVSL that extend in the first direction DR1.”) . With regards to claim 11 , the combined device of A_Park and B_Park teaches the display device of claim 10. The combined device of A_Park and B_Park does not teach that the third gate level further includes a gate line spaced apart from the first power voltage line, the gate line that receives a gate signal, and the gate line is connected to the second gate electrode through a contact hole. Jeon teaches a third gate level (see Jeon Fig. 10, first source metal layer; and see Jeon [0175]: “Referring to FIGS. 6, 10, and 11, the first source metal layer disposed on the second gate metal layer may include initialization voltage lines VIL, a k-th scan initialization line GILk, a k-th scan write line GWLk, a k-th PWM light emitting line PWELk, a first horizontal power line HVDL, a gate-off voltage line VGHL, a k-th sweep signal line SWPLk, a k-th scan control line GCLk, a k-th PAM light emitting line PAELk, a test signal line TSTL, and a third horizontal power line HVSL that extend in the first direction DR1.”) that includes a first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) that receives a first power voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) and a gate line (see Jeon Fig. 10, k-th scan write line GWLk) spaced apart from the first power voltage line (see Jeon Fig. 10) , the gate line that receives a gate signal (see Jeon [0125]: “The second transistor T2 is turned on by a k-th scan write signal of a k-th scan write line GWLk”) , and the gate line is connected to the second gate electrode through a contact hole (see Jeon Fig. 17, where k-th scan write line GWLk is shown to connect to fourth sub-gate electrode G42 through first gate contact hole GCT1.); and a date conductive layer (see Jeon Fig. 10, second source metal layer; and see Jeon [0176]: “The second source metal layer disposed on the first source metal layer may include the j-th data line DLj, the first vertical power line VVDL, and the first PAM data line RDL that extend in the second direction DR2.”) disposed on the third gate level (see Jeon Fig. 10 and Jeon [0176]) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the third gate level and data conductive level of A_Park and B_Park with the third gate level and data conductive level taught by Jeon in order to further control light leakage phenomena (see Jeon [0289]: “In one or more embodiments, by replacing the mask forming an alignment key with the active layer ACT, the light blocking layer disposed between the buffer layer BF and the gate insulating layer 130 may be omitted. When the light blocking layer is omitted, one mask process may be additionally omitted. In this case, a light leakage phenomenon emitted from the display device 10 may be controlled through the first gate metal layer.”) and simplify the manufacture process (see Jeon [0042]: “Since the second gate metal layer includes a low driving voltage wiring to which a low driving voltage is applied to an area where the upper capacitor electrode is not disposed, the number of masks may be reduced. Accordingly, the manufacturing cost of the display device may be reduced and the manufacturing process thereof may be simplified.”). With regards to claim 12 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 11, wherein the data conductive level (see Jeon Fig. 10, second source metal layer; and see Jeon [0176]: “The second source metal layer disposed on the first source metal layer may include the j-th data line DLj, the first vertical power line VVDL, and the first PAM data line RDL that extend in the second direction DR2.”) includes a data line (see Jeon Fig. 10, j-th data line DLj) that receives a data voltage (see Jeon [0114]: “The source driver 200 converts the digital video data DATA into analog PWM data voltages and outputs the analog PWM data voltages to the PWM data lines DL.”) , and the data line is connected to the second active pattern layer (see Jeon Fig. 17, where the j-th data line DLj is shown to connect to the second source electrode S2 of the active layer ACT through data contact holes DCT1 and DCT2.) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being obvious over A_Park, B_Park, and Jeon in view of Yu et al. (Pub. No.: US 20230162679 A1), hereinafter as Yu, using Yu's foreign priority date of Nov. 25, 2021. The applied references Jeon and Yu have a common applicant with the instant application. Based upon the earlier effectively filed date of the references, they constitute prior art under 35 U.S.C. 102(a)(2). With regards to claim 7 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 6. The combined device of A_Park, B_Park, and Jeon does not teach that the data conductive level includes: a second power voltage line that receives the first power voltage; a second reference voltage line that receives the reference voltage; and a data line that receives a data voltage, the second power voltage line is connected to the first power voltage line, and the second reference voltage line is connected to the first reference voltage line. Yu teaches a data conductive level (see Yu Fig. 15&16, second data conductive layer; and see Yu [0163]: “the second data conductive layer may include the data line 171, the third driving low voltage line 176-2 (hereinafter also referred to as a driving low voltage line), the third reference voltage line 174-2, the third initialization voltage line 175-2, and the second anode connection portion ACN2.”) that includes: a second power voltage line (see Yu Fig. 15&16, third driving low voltage line 176-2) that receives a first power voltage (see Yu [0061]: “and the driving low voltage line 176 may apply a common voltage ELVSS.”) ; a second reference voltage line (see Yu Fig. 15&16, third reference voltage line 174-2) that receives a reference voltage (see Yu [0061]: “the reference voltage line 174 may apply a reference voltage VREF,” which is connected to a second reference line 174-1 which is connected to the third reference line 174-2) ; and a data line (see Yu Fig. 15&16, data line 171) that receives a data voltage (see Yu [0061]: “The data line 171 may transmit a data voltage DATA generated by a data driver (not shown),”) , the second power voltage line is connected to the first power voltage line (see Yu [0164]: “the third driving low voltage line 176-2 may be connected to the second auxiliary connection portion CN172 and the second driving low voltage line 176-1 through the opening OP2,”) , and the second reference voltage line is connected to the first reference voltage line (see Yu [0164]; “the third reference voltage line 174-2 may be connected to the second reference voltage line 174-1 and the third auxiliary connection part CN174 through the opening OP2,”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the data conductive level of A_Park, B_Park, and Jeon with the data conductive level taught by Yu in order to connect the reference voltage through all layers below the light element. With regards to claim 8 , the combined device of A_Park, B_Park, Jeon, and Yu teaches the display device of claim 7, wherein each of the second power voltage line (see Yu Fig. 15&16, third driving low voltage line 176-2) , the second reference voltage line (see Yu Fig. 15&16, third reference voltage line 174-2) , and the data line (see Yu Fig. 15&16, data line 171) extends in a second direction intersecting the first direction (see Yu Fig. 15&16, where the lines extend vertically while the lines from Jeon’s first source metal layer extend horizontally, therefore intersecting.) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being obvious over A_Park and B_Park in view of Lee et al. (Pub. No.: US 20230363216 A1), hereinafter as Lee, using Lee's foreign priority date of May 11, 2016. The applied reference Lee has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). With regards to claim 14 , the combined device of A_Park and B_Park teaches the display device of claim 1. The combined device of A_Park and B_Park does not teach that the third gate level includes a low-resistance metal. Lee teaches a third gate level (see Lee Fig. 10, shielding layer 178 and auxiliary connection layer 179) that includes a low-resistance metal (see Lee [0093]: “For example, the shielding layer 178 and the auxiliary connection layer 179 may include a multi-layered structure including Ti/Al/Ti.”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the third gate level of A_Park and B_Park with the material taught by Lee in order to prevent voltage drop due to internal resistance. With regards to claim 15 , the combined device of A_Park and B_Park teaches the display device of claim 1. The combined device of A_Park and B_Park does not teach that the third gate level has a multi-layer structure including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer stacked with each other. Lee teaches a third gate level (see Lee Fig. 10, shielding layer 178 and auxiliary connection layer 179) that has a multi-layer structure including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer stacked with each other (see Lee [0093]: “For example, the shielding layer 178 and the auxiliary connection layer 179 may include a multi-layered structure including Ti/Al/Ti.”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the third gate level of A_Park and B_Park with the material taught by Lee in order to in order to prevent voltage drop due to internal resistance. This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Claims 16-20 and 23-25 are rejected under 35 U.S.C. 103 as being obvious over A_Park in view of B_Park, further in view of Jeon. The applied reference Jeon has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). With regards to claim 16 , A_Park teaches a display device comprising: a first transistor (see A_Park Fig. 2, first thin-film transistor T1) that generates a driving current (see A_Park [0064]: “In this case, the first thin-film transistor T1 may be coupled (e.g., connected) to an organic light-emitting diode 200 to serve as a driving thin-film transistor that drives the organic light-emitting diode 200.”) , the first transistor including: a part of a first active pattern layer (see A_Park Fig. 2, first semiconductor layer A1) disposed on a substrate (see A_Park Fig. 2, substrate 100) , and a first gate electrode (see A_Park Fig. 2, first gate electrode G1) disposed on the first active pattern layer and partially overlapping the first active pattern layer (see A_Park Fig. 2) ; and a first capacitor (see A_Park Fig. 2, storage capacitor Cst) including: the first gate electrode, and a capacitor electrode (see A_Park Fig. 2, top electrode CE2) disposed on the first gate electrode and overlapping the first gate electrode (see A_Park Fig. 2) . A_Park does not teach a second capacitor including: the capacitor electrode, and a part of a first power voltage line disposed on the capacitor electrode and overlapping the capacitor electrode, the first power voltage line that receives a first power voltage; a data conductive level disposed on the first power voltage line and including an anode connection pattern layer; an inorganic insulating layer disposed between the capacitor electrode and the data conductive level , and covering the capacitor electrode; and a light emitting element disposed on the data conductive level and including an anode electrode connected to the anode connection pattern layer and a cathode electrode that receives a second power voltage different from the first power voltage. B_Park teaches a second capacitor (see B_Park Fig. 5, first storage capacitor CST1) including: a capacitor electrode (see B_Park Fig. 5, first gate electrode G1) , and a part of a first power voltage line (see B_Park Fig. 5, first power voltage line PVL1) disposed on the capacitor electrode and overlapping the capacitor electrode (see B_Park Fig. 5) , the first power voltage line that receives a first power voltage (see B_Park [0053]: “The first power voltage lines PVL1 may transfer a first light-emitting power voltage ELVDD provided from the main driver 200 to the pixels P.”) ; a data conductive level (see B_Park Fig. 5, third conductive layer; and see B_Park [0119]: “Referring to FIGS. 5 and 10, a third conductive layer may be formed on the substrate 110 having the contact holes CH, the first via holes VH1 and the second via holes VH2 and patterned to form a third conductive pattern.”; and Park [0120]: “The third conductive pattern may include an m-th data line DLm, a second power voltage line PVL2, a first electrode pattern EP1, a second electrode pattern EP2 and a third electrode pattern EP3.”) disposed on the first power voltage line (see B_Park Fig. 5) ; an inorganic insulating layer (see B_Park Fig. 5, third insulation layer 140; and see B_Park [0114]: “The third insulation layer 140 may include an inorganic insulation layer including silicon nitride, silicon oxide, silicon oxynitride or the like, an organic insulation layer including an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin or the like, or combination thereof.”) disposed between the capacitor electrode and the data conductive level (see B_Park Fig. 5) , and covering the capacitor electrode (see B_Park Fig. 5) ; and a light emitting element (see B_Park Fig. 5, organic light-emitting diode OLED) disposed on the data conductive level (see B_Park Fig. 5 and B_Park [0119], third conductive layer) and including an anode electrode (see B_Park Fig. 5, first diode electrode E1; see Park [0059]: “The first diode electrode E1 may be an anode, and the second diode electrode E2 may be a cathode.”) and a cathode electrode (see B_ Park Fig. 5, second diode electrode E2; see B_Park [0059]: “The first diode electrode E1 may be an anode, and the second diode electrode E2 may be a cathode.”) that receives a second power voltage different from the first power voltage (In applicant’s Fig. 2, the light emitting element LED is electrically written as a diode. Therefore, the anode electrode is associated with the p-side and the cathode electrode is associated with the n-side, especially since the cathode electrode receives the second power voltage ELVSS. In B_Park Fig. 2, organic light-emitting diode OLED is electrically written as a diode, with first diode electrode E1 before the organic light-emitting diode OLED and second diode electrode E2 after it. Therefore, the first diode electrode E1, which is the anode electrode, is associated with the p-side and the second diode electrode E2, which is the cathode electrode, is associated with the n-side. According to page 292 of Livingston, “Current flow is easy when a p-n junction is forward biased (attracting majority carriers to junction) and hard when the junction is reversed biased (attracting minority carriers to junction).” With this, it would have been obvious for a person having ordinary skill in the art to supply the first diode electrode E1 with a higher voltage level than the second diode electrode E2 in order for the organic light-emitting diode OLED to function.) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the top layers disposed upon the capacitor electrode of A_Park with the top layers (the second conductive pattern through the OLED) taught by B_Park in order to assign the TFTs jobs (by adding a data line, see A_Park [0064]: “The second thin-film transistor T2 may be coupled (e.g., connected) to a data line to serve as a switching thin-film transistor.”) and to increase capacitance by adding an additional capacitor. The combination of A_Park and B_Park does not teach a data conductive level including an anode connection pattern layer and an anode electrode that is connected to the anode connection pattern layer. Jeon teaches a data conductive level (see Jeon Fig. 10, second source metal layer; and see Jeon [0176]: “The second source metal layer disposed on the first source metal layer may include the j-th data line DLj, the first vertical power line VVDL, and the first PAM data line RDL that extend in the second direction DR2.” and “In addition, the second source metal layer may further include a first anode connection electrode ANDE1 and a second power connection electrode VDCE.”) including an anode connection pattern layer (see Jeon Fig. 20, first anode connection electrode ANDE1) and an anode electrode (see Jeon Fig. 20, anode pad electrode APD) that is connected to the anode connection pattern layer (see Jeon Fig. 20) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the data conductive level of A_Park and B_Park with the data conductive level taught by Jeon in order to in order to have all the required wiring to drive the circuit while also saving space. With regards to claim 17 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 16, wherein the inorganic insulating layer (see B_Park Fig. 5, third insulation layer 140) directly contacts the first power voltage line (see B_Park Fig. 5, first power voltage line PVL1, which is part of the second conductive pattern (see B_Park [0110])) . With regards to claim 18 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 16, further comprising: an organic insulating layer (see B_Park Fig. 5, fourth insulation layer 150; and see B_Park [0127]: “The fourth insulation layer 150 may include an organic insulation layer, which may include an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin or the like, and/or an inorganic insulation layer, which includes silicon nitride, silicon oxide, silicon oxynitride or the like, or a combination thereof.”) disposed between the data conductive level (see Jeon Fig. 10, second source metal layer; and see Jeon [0176]) and the anode electrode (see B_Park Fig. 5, first diode electrode E1; see Park [0059]: “The first diode electrode E1 may be an anode, and the second diode electrode E2 may be a cathode.”) ; and a pixel defining layer (see B_ Park Fig. 5, fifth insulation layer 160) disposed on the organic insulating layer and covering an edge portion of the anode electrode (see B_ Park Fig. 5) , wherein any organic insulating layer other than the organic insulating layer is not disposed between the organic insulating layer and the pixel defining layer (see B_Park Fig. 5, where fifth insulation layer 160 is directly on top of fourth insulation layer 150, with no other insulating layer in between. Also, fourth insulation layer 150 may comprise of two layers, one organic and the other inorganic (see B_Park [0127]), with the inorganic layer disposed between the organic layer and fifth insulation layer 160. This structure also teaches the limitation.) . With regards to claim 19 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 16. The combined device of A_Park, B_Park, and Jeon does not teach a first initialization voltage line that receives a first initialization voltage; a second initialization voltage line that receives a second initialization voltage; a first reference voltage line that receives a reference voltage; a gate line that receives a gate signal; and a bias voltage line that receives a bias voltage. However, Jeon further teaches a first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) that receives a first power voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) ; a first initialization voltage line (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines shown) that receives a first initialization voltage (because the initialization voltage lines are completely separate (as shown in Image A), they would receive two separate initialization voltages.) ; a second initialization voltage line (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines shown) that receives a second initialization voltage (because the initialization voltage lines are completely separate (as shown in Image A), they would receive two separate initialization voltages.) ; a first reference voltage line (see Jeon Fig. 10, third horizontal power line HVSL) that receives a reference voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) ; a gate line (see Jeon Fig. 10, k-th scan write line GWLk) that receives a gate signal (see Jeon [0125]: “The second transistor T2 is turned on by a k-th scan write signal of a k-th scan write line GWLk”) ; and a bias voltage line (see Jeon Fig. 10, k-th scan write line GWLk) that receives a bias voltage (see Jeon [0110]: “The sweep signal driver 113 may output PWM light emitting signals to the PWM light emitting lines PWEL and output sweep signals to the sweep signal lines SWPL according to the first light emitting control signal.”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the aforementioned layer of A_Park, B_Park, and Jeon with the layer taught by Jeon in order to in order to have all the required wiring to drive the circuit while also saving space. With regards to claim 20 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 19, wherein each of the first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) , the gate line (see Jeon Fig. 10, k-th scan write line GWLk) , the first and second initialization voltage lines (see Jeon Fig. 10, initialization voltage lines VIL, where there are two separate initialization voltage lines shown) , the first reference voltage line (see Jeon Fig. 10, third horizontal power line HVSL) , and the bias voltage line (see Jeon Fig. 10, k-th sweep signal line SWPLk) extends in a first direction (see Jeon [0175]: “Referring to FIGS. 6, 10, and 11, the first source metal layer disposed on the second gate metal layer may include initialization voltage lines VIL, a k-th scan initialization line GILk, a k-th scan write line GWLk, a k-th PWM light emitting line PWELk, a first horizontal power line HVDL, a gate-off voltage line VGHL, a k-th sweep signal line SWPLk, a k-th scan control line GCLk, a k-th PAM light emitting line PAELk, a test signal line TSTL, and a third horizontal power line HVSL that extend in the first direction DR1.”) . With regards to claim 23 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 16, further comprising: a second transistor (see A_Park Fig. 2, second thin-film transistor T2) including a part of a second active pattern layer (see A_Park Fig. 2, second semiconductor layer A2) and a second gate electrode (see A_Park Fig. 2, second gate electrode G2) partially overlapping the second active pattern layer (see A_Park Fig. 2) . With regards to claim 24 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 23. The combined device of A_Park, B_Park, and Jeon does not teach a gate line that receives a gate signal, wherein the gate line is connected to the second gate electrode through a contact hole. However, Jeon further teaches a first power voltage line (see Jeon Fig. 10, first horizontal power line HVDL) that receives a first power voltage (see Jeon [0179]: “In the present specification, the first horizontal power line HVDL and the first vertical power line VVDL may be lines to which the first power voltage (‘VDD1’ in FIG. 4) is applied, the second power line VDL2 may be a line to which the second power voltage (‘VDD2’ in FIG. 4) is applied, and the third power line VSSL and the third horizontal power line HVSL may be lines to which the third power voltage (‘VSS’ in FIG. 4) is applied.”) and a gate line (see Jeon Fig. 10, k-th scan write line GWLk) that receives a gate signal (see Jeon [0125]: “The second transistor T2 is turned on by a k-th scan write signal of a k-th scan write line GWLk”) , wherein the gate line is connected to the second gate electrode through a contact hole (see Jeon Fig. 17, where k-th scan write line GWLk is shown to connect to fourth sub-gate electrode G42 through first gate contact hole GCT1.) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the aforementioned layer of A_Park, B_Park, and Jeon with the layer taught by Jeon in order to in order to have all the required wiring to drive the circuit while also saving space. With regards to claim 25 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 24, wherein the data conductive level (see Jeon Fig. 10, second source metal layer; and see Jeon [0176]: “The second source metal layer disposed on the first source metal layer may include the j-th data line DLj, the first vertical power line VVDL, and the first PAM data line RDL that extend in the second direction DR2.” and “In addition, the second source metal layer may further include a first anode connection electrode ANDE1 and a second power connection electrode VDCE.”) includes a data line (see Jeon Fig. 10, j-th data line DLj) that receives a data voltage (see Jeon [0114]: “The source driver 200 converts the digital video data DATA into analog PWM data voltages and outputs the analog PWM data voltages to the PWM data lines DL.”) , and the data line is connected to the second active pattern layer (see Jeon Fig. 17, where the j-th data line DLj is shown to connect to the second source electrode S2 of the active layer ACT through data contact holes DCT1 and DCT2.) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being obvious over A_Park, B_Park, and Jeon in view of Yu. The applied references Jeon and Yu have a common applicant with the instant application. Based upon the earlier effectively filed date of the references, they constitute prior art under 35 U.S.C. 102(a)(2). With regards to claim 21 , the combined device of A_Park, B_Park, and Jeon teaches the display device of claim 20. The combined device of A_Park, B_Park, and Jeon does not teach that the data conductive level includes: a second power voltage line that receives the first power voltage; a second reference voltage line that receives the reference voltage; and a data line that receives a data voltage, the second power voltage line is connected to the first power voltage line, and the second reference voltage line is connected to the first reference voltage line. Yu teaches a data conductive level (see Yu Fig. 15&16, second data conductive layer; and see Yu [0163]: “the second data conductive layer may include the data line 171, the third driving low voltage line 176-2 (hereinafter also referred to as a driving low voltage line), the third reference voltage line 174-2, the third initialization voltage line 175-2, and the second anode connection portion ACN2.”) includes: a second power voltage line (see Yu Fig. 15&16, third driving low voltage line 176-2) that receives the first power voltage (see Yu [0061]: “and the driving low voltage line 176 may apply a common voltage ELVSS.”) ; a second reference voltage line (see Yu Fig. 15&16, third reference voltage line 174-2) that receives the reference voltage (see Yu [0061]: “the reference voltage line 174 may apply a reference voltage VREF,” which is connected to a second reference line 174-1 which is connected to the third reference line 174-2) ; and a data line (see Yu Fig. 15&16, data line 171) that receives a data voltage (see Yu [0061]: “The data line 171 may transmit a data voltage DATA generated by a data driver (not shown),”) , the second power voltage line is connected to the first power voltage line (see Yu [0164]: “the third driving low voltage line 176-2 may be connected to the second auxiliary connection portion CN172 and the second driving low voltage line 176-1 through the opening OP2,”) , and the second reference voltage line is connected to the first reference voltage line (see Yu [0164]; “the third reference voltage line 174-2 may be connected to the second reference voltage line 174-1 and the third auxiliary connection part CN174 through the opening OP2,”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the data conductive level of A_Park, B_Park, and Jeon with the data conductive level taught by Yu in order to connect the reference voltage through all layers below the light element. With regards to claim 22 , the combined device of A_Park, B_Park, Jeon, and Yu teaches the display device of claim 21, wherein each of the second power voltage line (see Yu Fig. 15&16, third driving low voltage line 176-2) , the second reference voltage line (see Yu Fig. 15&16, third reference voltage line 174-2) , and the data line (see Yu Fig. 15&16, data line 171) extends in a second direction intersecting the first direction (see Yu Fig. 15&16, where the lines extend vertically while the lines from Jeon’s first source metal layer extend horizontally, therefore intersecting.) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 5712721657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.T.B./Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/624,825 Page 2 Art Unit: 2818 Application/Control Number: 18/624,825 Page 4 Art Unit: 2818 Application/Control Number: 18/624,825 Page 5 Art Unit: 2818 Application/Control Number: 18/624,825 Page 6 Art Unit: 2818 Application/Control Number: 18/624,825 Page 7 Art Unit: 2818 Application/Control Number: 18/624,825 Page 8 Art Unit: 2818 Application/Control Number: 18/624,825 Page 9 Art Unit: 2818 Application/Control Number: 18/624,825 Page 10 Art Unit: 2818 Application/Control Number: 18/624,825 Page 11 Art Unit: 2818 Application/Control Number: 18/624,825 Page 12 Art Unit: 2818 Application/Control Number: 18/624,825 Page 13 Art Unit: 2818 Application/Control Number: 18/624,825 Page 14 Art Unit: 2818 Application/Control Number: 18/624,825 Page 15 Art Unit: 2818 Application/Control Number: 18/624,825 Page 16 Art Unit: 2818 Application/Control Number: 18/624,825 Page 17 Art Unit: 2818 Application/Control Number: 18/624,825 Page 18 Art Unit: 2818 Application/Control Number: 18/624,825 Page 19 Art Unit: 2818 Application/Control Number: 18/624,825 Page 20 Art Unit: 2818 Application/Control Number: 18/624,825 Page 21 Art Unit: 2818 Application/Control Number: 18/624,825 Page 22 Art Unit: 2818 Application/Control Number: 18/624,825 Page 23 Art Unit: 2818 Application/Control Number: 18/624,825 Page 24 Art Unit: 2818 Application/Control Number: 18/624,825 Page 25 Art Unit: 2818 Application/Control Number: 18/624,825 Page 26 Art Unit: 2818 Application/Control Number: 18/624,825 Page 27 Art Unit: 2818 Application/Control Number: 18/624,825 Page 28 Art Unit: 2818 Application/Control Number: 18/624,825 Page 29 Art Unit: 2818 Application/Control Number: 18/624,825 Page 30 Art Unit: 2818 Application/Control Number: 18/624,825 Page 31 Art Unit: 2818 Application/Control Number: 18/624,825 Page 32 Art Unit: 2818 Application/Control Number: 18/624,825 Page 33 Art Unit: 2818
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