DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant election, without traverse, of Species 1 shown in Figs. 1-9 in the Response (filed 08/24/26) to Restriction Requirements has been acknowledged.
Applicant stated that Claims 1-20 are directed to the chosen species. However, Claim 13, citing “a via pad below the semiconductor substrate” belongs to Species 2 (shown in Fig. 10, see paragraph 0055 of a published application US 2025/0079296), Claim 16, citing: “a buffer chip”, etc., belongs to Species 3 (shown in Figs. 11, see paragraphs 0060-0061 of the published application); Claim 17 depends on Claim 16; Claim 19, citing: “a connection pad”, is described by paragraph 0064 with respect to Fig. 11B (related to Species 3).
Status of Claims
Claims 13, 16-17, and 19 are withdrawn from further consideration as being directed to nonelected inventions.
Claims 1-12, 14-15, 18, and 20 are examined on merits herein.
Specification
The disclosure is objected to because of the following informalities:
Specification is inconsistent with some definitions. As such, paragraph 0027 of the published application teaches that interconnection region 120 is on device region 110, while paragraph 0030 teaches that a lower interconnection 126 of interconnection region 120 is in device region 110.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-7, 9-10, 12, 14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hutta et al. (US 2011/0266679) in view of Mori (JP H07201983).
In re Claim 1, Hotta teaches a semiconductor device, comprising (Fig. 1):
a semiconductor substrate 1 (paragraph 0049);
a device region – with transistors nMIS and pMIS (paragraph 0049) on the semiconductor substrate 1;
an interconnection region – including dielectric layers from 14 to 16a (paragraphs 0050-0053) including a lower interconnection – one of M1 through M4 (paragraphs 0052-0053, 0055) on the device region;
an insulating structure – including insulating layers 19 and 23 (paragraphs 0044-0045) – on the interconnection region;
lower conductive patterns M5 (paragraph 0051) in the insulating structure (in layer 19a);
a first conductive via 18a (paragraph 0053) electrically connecting at least one of the lower conductive patterns M5 to the lower interconnection – to M4 – of the interconnection region;
upper conductive patterns M6 (paragraph 0051) on the insulating structure; and
second conductive vias 24 (paragraph 0056) in the insulating structure (in layer 23) and electrically connecting the upper conductive patterns M6 to the at least one of the lower conductive patterns M5, wherein
the first conductive via 18a comprises a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer (all vias, called “coupling holes”, are made similar to via 11, which comprises a barrier on a lower surface and a side surface of a corresponding opening/hole and a metal filling a remining part – see Fig. 4 and paragraphs 0070, 0061, 0075, 0078), wherein
the second conductive vias 24 respectively comprise a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer (paragraph 0082), and wherein
the upper conductive patterns M6 respectively comprise:
a third metal layer 27 (paragraph 0040) on the second metal layer (of via 24);
an upper metal layer 26 (paragraph 0040) on the third metal layer 27; and
an upper anti-reflective layer 28 (paragraph 0040) on the upper metal layer 26.
Hutta does not teach that the upper conductive patterns M6 comprise a third barrier layer extending from the second barrier layer and on a portion of an upper surface of the insulating structure, where the third metal layer 27 is not only on the second metal layer 25, but also on the third barrier layer and extends from the second metal layer (e.g., made from material of metal 25). Moreover, Hutta teaches that his third metal layer 27 comprises TiN (paragraph 0040) while a second metal layer 25 is made from W (paragraph 0056)
Mori teaches (Fig. 17) an upper conductive pattern comprises a third barrier layer (being an upper horizontal portion of 18 made from Ti, page 6 last paragraph) extending from a second barrier layer (comprising a vertical portion of 18 of Ti) and on a portion of an upper surface of an insulation structure 12 (page 6 paragraph five from the top), wherein a third metal layer 16a (made from TiN, page 7 paragraph 4) is on a second metal layer 19 (made from TiN, page 6 last paragraph) and extending from the second metal layer 19. Mori further teaches an upper metal layer 14 (made from Cu, page 6 paragraph 6) on the third metal layer 16a and an upper anti-reflective layer 16c (made from TiN) on the upper metal layer 14.
Hutta and Mori teach analogous arts directed to interconnects, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Hutta device in view of the Mori teaching, since they are from the same field of endeavor, and Mori created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Hutta device by substituting its second conductive via and at least a lower portion of the upper conductive patterns with those that are structurally made per Mori (but preserving thicknesses and/or materials taught by Hutta where possible, since Mori does not teach thicknesses, while the device with materials taught by Hutta also successfully operates), and where the upper conductive pattern comprises a third barrier layer extending from the second barrier layer and on a portion of an upper surface of the insulation structure, wherein the third metal layer 27 (of Hutta or 16a of Mori) is on the second metal layer 25 (of Hutta; or 19 of Mori) extending from the second metal layer, if such modification would either simplify creation the connection structure (Mori, Abstract) or would be preferred by the manufacturer for other reasons: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 2, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above.
Hutta further teaches a thickness of the upper metal layer 26 (Fig. 1, paragraph 0058) is 1000 nm and a thickness of the antireflective layer 28 (in the range 100 nm-300 nm, paragraph 0058), but does not state that the thickness of layer 26 is greater than a thickness of the third metal layer 27 – he does not teach a thickness of layer 27, though he shows in Fig. 1 that layer 27 is thinner than layer 28 and layers 27 and 28 are made from a same material (paragraphs 0058, 0084)
Although Hutta does not state that his drawings are made in scale, one of ordinary skill in the art before the effective date of filing the application would have created layer 27, based on Fig. 1, being thinner than layer 28, and, accordingly thinner than layer 26, in order to enable such parameter of layer 27 as its thickness. With this modification, Hutta/Mori makes the limitation of Claim 2 – obvious.
In re Claim 4, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above.
Hutta further teaches that the insulating structure comprises (Fig. 1):
a first upper insulating layer 19a (from a low-k dielectric, paragraph 0044) on side surfaces and upper surfaces of the lower conductive patterns M5;
a second upper insulating layer 22 (from SiN, paragraph 0045) on the first upper insulating layer 19a; and
a third upper insulating layer 23 (from SiO2, paragraph 0057) on the second upper insulating layer 22, and wherein
a material of the second upper insulating layer 22 is different from materials of the first 19a and third 23 upper insulating layers.
In re Claim 6, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above.
Hutta teaches that the device further comprising (Fig. 1):
an interlayer insulating layer 17 (paragraph 0061) between the interconnection region (comprising dielectrics from 14 to 16a) and the insulating structure (with 19a and M5), wherein
the lower conductive patterns M5 respectively comprise the first barrier layer (paragraphs 0051, 0078) on a portion of an upper surface of the interlayer insulating layer 17, the first metal layer (of Cu, paragraph 0078) on the first barrier layer on the portion of the upper surface of the interlayer insulating layer – e.g., on layer 17.
Hutta does not teach that the lower conductive patterns further comprise a lower metal layer on the first metal layer, and a lower anti-reflective layer on the lower metal layer.
Mori teaches a conductive pattern comprising (Fig. 17) a first barrier layer (being an upper horizontal portion of 18 made from Ti, page 6 last paragraph) on a portion of an upper surface of an insulation structure 12 (page 6 paragraph five from the top), a first metal layer 16a (made from TiN, page 7 paragraph 4) on the first barrier layer 18 and on the portion of the upper surface of the insulation structure 12, a lower metal layer 14 (made from Cu, page 6 paragraph 6) on the first metal layer 16a and a lower anti-reflective layer 16c (made from TiN) on the lower metal layer 14.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Hutta/More device of Claim 1 by creating the lower conductive pattern based on the Mori teaching (and using a step of substituting the lower conductive pattern of Hutta), if such modification would either simplify creation of the lower conductive pattern (Mori, Abstract) or would be just preferred by the manufacturer for other reasons: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 7, Hutta/Mori teaches the semiconductor device of Claim 6 as cited above, wherein the lower conductive pattern is made similar to the upper conductive pattern of Claim 1. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create a thickness of the lower metal layer being greater than a thickness of the first metal layer on the upper surface of the interlayer insulating layer for the same reason that is stated for Claim 2 for the upper conductive patterns – e.g., for enabling thicknesses of various sublayers of the lower conductive patterns.
In re Claim 9, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above, Hutta further teaches that (Fig. 1) the upper metal layer 26 is made from Al (paragraph 0049) and the second metal layer 25 is made from W (paragraph 0056), and as such, the upper metal layer and the second metal layer comprise different materials.
In re Claim 10, Hutta/Mori teaches the semiconductor device of Claim 9 as cited above, wherein, as shown for Claim 9, the upper metal layer comprises aluminum (Al), and wherein the second metal layer includes comprises tungsten (W).
In re Claim 12. Hutta/Mori teaches the semiconductor device of Claim 1 as cited above.
Hutta teaches that the device further comprising (Fig. 1):
a protective layer 30A (paragraph 0041) on the insulating structure (comprise layer 23) and the upper conductive patterns M6;
a first passivation layer 30B (paragraph 0041) on the protective layer 30A; and
a second passivation layer 32 (paragraph 0042) on the first passivation layer 30B.
In re Claim 14, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above, wherein at least a third barrier layer is added – as a lower layer – into the upper conductive patterns M6 of Hutta.
Hutta/Mori further teaches (Hutta, Fig. 1) that the upper metal layer 26 is spaced apart from the upper surface of the insulating structure – comprising layer 23.
In re Claim 18, Hotta teaches a semiconductor device, comprising (Fig. 1):
an insulating structure – comprising insulating layers 19a and 23 (paragraphs 0044-0045) on a semiconductor substrate 1 (paragraph 0049);
lower conductive patterns M5 (paragraph 0051) in the insulating structure;
first conductive vias 18a (paragraph 0053) on lower surfaces of the lower conductive patterns M5;
an upper conductive pattern M6 (paragraph 0051) on the insulating structure; and
second conductive vias 24 (paragraph 0056) in the insulating structure and electrically connecting the upper conductive pattern M6 to the lower conductive patterns M5, wherein
the first conductive vias 18a respectively comprise a first metal layer and a first barrier layer covering a lower surface and a side surface of the first metal layer (all vias, called “coupling holes”, are made similar to via 11, which comprises a barrier on a lower surface and a side surface of a corresponding opening/hole and a metal filling a remining part – see Fig. 4 and paragraphs 0070, 0061, 0075, 0078), wherein
the second conductive vias 24 respectively comprise a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer (paragraph 0082), and wherein
the upper conductive pattern M6 comprises:
a first conductive layer 27 (paragraph 0040);
a second conductive layer 26 (paragraph 0040) on the first conductive layer 27; and
a third conductive layer 28 (paragraph 0040) on the second conductive layer 26.
Hutta does not teach that the first conductive layer extends from the second conductive vias.
Mori teaches (Fig. 17) a first conductive layer 16a, 18 (page 6 last paragraph and page 7 paragraph 4) extending from a second conductive via 18, 19 (column 6 last paragraph).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Hutta device by substituting the first conductive layer to that that is extending from the second conductive via (per Mori), if this would either simplify the manufacturing process (Mori, Abstract) or just preferred by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 20, Hutta/Mori teaches the semiconductor device of Claim 18 as cited above, wherein the first conductive layer (made per Mori) comprises (Mori, Fig. 17) a third metal layer 16 continuously extending from the second metal layer 18 and a third barrier layer 18 (as a top horizontal portion of 18) continuously extending from a second barrier layer (which is a 18 vertical portion).
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hutta/Mori in view of Choi et al (US 2021/0280541).
In re Claim 5, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above, wherein the upper conductive patterns comprises the upper metal layer 26 on the third metal layer 27, but does not teach an upper barrier layer between the upper metal layer 26 and the third metal layer 27. However, Hutta teaches that the third metal layer is made from TiN (paragraph 0040), which is a well-known material used for a diffusion barrier.
Choi teaches (Fig. 4, paragraph 0035) a barrier layer 67 created as a stack of alternating layers Ti and TiN.
Hutta/Mori and Choi teach analogous arts directed to a layer created from TiN, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Hutta/Mori device in view of the Choi device, since they are from the same field of endeavor, and Choi created a successfully operated device.
It4ouldd have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Hutta/More device of Claim 1 by substituting TiN layer 27 with TiN/Ti/TiN layer (disposed on Ti barrier – per Mori), creating by that an upper barrier layer Ti/TiN between layers 26 and 27 of Hutta, wherein it is preferrable having a barrier layer comprising an alternating stack of Ti/TiN layers (per Choi). See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 11, Hutta/Mori teaches the semiconductor device of Claim 1 as cited above, including the upper and lower conductive patterns
Hutta does not teach that respective thicknesses of the upper conductive patterns are greater than respective thicknesses of the lower conductive patterns.
Mori shows (Fig. 17) that a thickness of an upper conductive pattern (with layer 14) is greater that a thickness of a lower conductive pattern 13 but does not state that drawings are in scale.
Choi teaches (Fig. 1) that a thickness d2 of an upper conductive pattern 62 is greater than a thickness d1 of a lower conductive pattern 42 (paragraph 0025).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Hutta/Mori device by creating the upper conductive patterns with a greater thickness than that of the lower conductive pattern, where it is desirable reducing a thickness of the entire device by reducing thicknesses of the lower conductive patterns.
Allowable Subject Matter
Claims 3, 8, and 15 contain allowable subject matter and are objected by the current Office Action as being dependent on a rejected base Claim 1. Each of these claims would be allowed if amended to include all limitations of the base claim and all limitations of all intervening (if any) claims.
Reason for Indicating Allowable Subject Matter
Re Claim 3: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 3 as: “a thickness of the upper metal
layer is substantially equal to or smaller than a thickness of the third metal layer on the upper surface of the insulating structure”, in combination with all limitations of Claim 1.
Re Claim 8: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 8 as: “a thickness of the lower metal
layer is substantially equal to or smaller than a thickness of the first metal layer on the upper surface of the interlayer insulating layer”, in combination with all limitations of Claims 1 and 6, on which Claim 8 depends.
Re Claim 15. Although Cheng (US 2020/0365551) teaches an upper conductive pattern comprising a conductive oxide layer, this oxide layer is not disposed between an upper metal layer and an upper anti-reflective layer, as Claim 15 recites, and there is no motivation in changing a position of this oxide layer in the conductive pattern structure.
The prior arts of record include all prior arts cited above, as well as such prior arts as: Kikuchi et al. (US 2010/0255675), Choi et al. (US 2021/0305115), Saito et al. (US 2001/0045651), and Park (US 2010/0148290).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 09/02/26
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