Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 12/23/2025. The changes and remarks disclosed therein have been considered. Claims 1-7, 14-18 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung PG PUB 20220293177 (hereinafter Jung), In view of Park PG PUB 20120099364 (hereinafter Park).
Regarding independent claim 1, Jung teaches a memory device, comprising:
a plurality of word lines (WL1-WL5 in figure 11 of June, [0109] of Jung, “…the memory cell array 110a may include first to fifth word lines WL1 to WL5 extending in a first horizontal direction HD1, first to fifth bit lines BL1 to BL5 extending in a second horizontal direction HD2, and a plurality of memory cells MC11 to MC55…”) extending in a first direction;
a plurality of bit lines (BL1-BL5 in figure 11 of Jung) extending in a second direction crossing the first direction;
a plurality of memory cells (MC11-MC55 in figure 11 of Jung) disposed in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and
a circuit (120/130/140/150/160 in figure 2 of Jung) configured to apply a first voltage (e.g., voltage applied to selected BL) to a first bit line (BL3 in figure 11 of Jung) of a target memory cell (MC33 in figure 11 of Jung), which is an initialization target cell (“initialization” has been interpreted under BRI as a resistive-state conditioning/ programming operation performed on target memory cell prior to subsequent operation) among the plurality of memory cells, apply a second voltage (voltage applied to the WL3 in figure 11 of Jung, see figure 17 and [0125]-[0129] of Jung) to a first word line (WL3 in figure 11 of Jung) of the target memory cell (MC33 in figure 11 of Jung) and perform at least one of a first operation and a second operation, wherein the first operation and the second operation are configured to control the memory device, wherein the plurality of bit lines includes the first bit line (BL3 in figure 11 of Jung), and the plurality of word lines includes the first word line (WL3 in figure 11 of Jung), wherein the first operation includes applying a first adjustment voltage to a second bit line (BL2/BL4 in figure 11 of Jung) or a second word line (WL2/WL4 in figure 11 of Jung) connected to an adjacent initialized memory cell (MC32/MC34/MC23/MC43 in figure 11 of Jung) that is an initialized memory cell among adjacent initialization cells that share the first bit line or the first word line (Jung teaches in figures 8-10, [0046]-[0059] to apply voltages/pulses to adjacent unselected or adjacent initialized memory cells to compensate for disturbance effects associated with initialization/write operations. Jung teaches in figures 12, 14, 16 and [0083]-[0124] that grouped adjacent cells receive different adjustment voltages V1, V2, V3 depending on positional relationship relative to target cell). and wherein the plurality of bit lines includes the second bit line and the third bit line, and the plurality of word lines includes the second word line and the third word line (figure 11 of Jung teaches multiple WLs and BLs).
But Jung does not teach wherein the second operation includes applying a third voltage of an opposite polarity to the first voltage to a third bit line of a next target memory cell that is initialized after initialization of the target memory cell, and applying a fourth voltage of an opposite polarity to the second voltage to a third word line of the next target memory cell.
However, Park teaches subsequent initialization of another target cells by applying corresponding voltages to another bit line and another word line associated with subsequent target cell, using opposite initialization polarities/voltages, [0050]/[0051] of Park, “…When a logically "high" word line driving voltage is supplied to a first word line WL1 and a (n+1).sup.th word line WL.sub.n+1, and the first initialization voltage V1 is greater than the second initialization voltage V2, a first initialization path…Alternately, when a high word line driving voltage is supplied to the first word line WL1 and the (n+1).sup.th word line WL.sub.n+1, and the second initialization voltage V2 is greater than the first initialization voltage V1, a second initialization path…”).
Jung and Park are analogous art because they address the same field of endeavor: memory storage apparatuses control circuit designs and control methods therefor. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung and Park before him, to modify the grouped adjacent-cell adjustment scheme of Jung to include sequential opposite-polarity initialization operation scheme of Park, in order to reduce disturbance effects, improve initialization/programming reliability, maintain threshold/resistance distributions of adjacent cells, and improve over-all memory device operations ([0046]-[0059] of Jung).
Regarding claim 2, the combination of Jung and Park teaches the memory device of claim 1, wherein: in the first operation, the target memory cell (MC33 in figure 11 of Jung) and the adjacent initialized memory cell (MC23, MC43 in figure 11 of Jung) share the first bit line (selected BL in figure 11 of Jung, e.g., BL3 in figure 11 of Jung), and the first adjustment voltage (Jung teaches V1 is applied to GR1 in figure 12, [0115] of Jung, “…a first cell group GR1 may include adjacent memory cells MC23 and MC43 connected to the third bit line BL3, which is the same bit line connected to the selected memory cell MC33. Voltages across the memory cells in the first cell group GR1 may correspond to a first voltage V1…”, thus the compensation/adjustment voltage associated with GR1 is applied through WL2/WL4) is applied to the second word line (WL2 or WL4 in figure 11 of Jung) connected to the adjacent initialized memory cell (MC23 or MC43 in figure 11 of Jung).
Regarding claim 3, the combination of Jung and Park teaches the memory device of claim 2, wherein: a voltage difference between the first voltage (voltage applied to selected BL, BL3 in figure 11 of Jung) and the first adjustment voltage (compensation/adjustment voltage associated with GR1 is applied through WL2/WL4 in figure 11 of Jung) is less than a voltage difference between the first voltage and a ground voltage (Jung teaches using adjacent-cell compensation voltages smaller than full ground-referenced programming differentials, and adjustment voltage having magnitudes between full write voltages and ground, see [0104]-[0107] of Jung, [0046] of Jung, “…the amplitude of the dummy pulse may be less than that of the write pulse…”).
Regarding claim 4, the combination of Jung and Park teaches the memory device of claim 2, wherein: when the third voltage having a polarity opposite to the first voltage is applied to the first bit line following the first voltage, and the fourth voltage having a polarity opposite to the second voltage is applied to the first word line following the second voltage, in the first operation, second adjustment voltage having a polarity opposite to the first adjustment voltage is applied to the second word line (Park teaches sequential initialization operations using opposite polarities during successive initialization operations, see [0049]-[0052] of Park, [0061]-[0064] of Park, Park further teaches that initialization voltages V1 and V2 applied with opposite relative polarity relationships during different initialization condition, see figure 7 of Park. Jung teaches applying compensation voltages to neighboring groups during subsequent operation, Jung [0105] teaches applying -2V to word lines WL1/WL3, teaches in [0106] applying 0V and different compensation levels to adjacent groups, Jung in figure 9A-9C teaches sequential dummy pulse operation DP1/DP2 having different timing/amplitude relationships. Jung teaches in [0097] using a third dummy pulse with smaller amplitude. Thus Jung teaches compensation voltages V1-V3 having different relative levels, including negative and zero-valued compensation voltages applied to neighboring groups during subsequent operations, hereby suggesting opposite-polarity neighboring adjustment voltages depending on operation polarity. Accordingly, it would have been obvious to modify Park’s sequential initialization operations using Jung’s opposite polarity neighboring compensation techniques to reduce disturbance effects and stabilize adjacent initialized memory cells).
Regarding claim 5, the combination of Jung and Park teaches the memory device of claim 1, wherein: in the first operation, the target memory cell (MC33 in figure 11 of Jung) and the adjacent initialized memory cell (MC32, MC34 in figure 11 of Jung) share the first word line (selected WL in figure 11 of Jung, e.g., WL3 in figure 11 of Jung), and the first adjustment voltage (Jung teaches V1 is applied to GR1 in figure 12, [0110] of Jung, “…adjacent memory cells MC32 and MC34 connected to the third word line WL3, which is the same word line connected to the selected memory cell MC33…”) is applied to the second bit line (BL2 or BL4 in figure 11 of Jung) connected to the adjacent initialized memory cell (MC32 or MC34 in figure 11 of Jung).
Regarding claim 6, the combination of Jung and Park teaches the memory device of claim 5, wherein: a voltage difference between the second voltage (voltage applied to selected WL) and the first adjustment voltage (the compensation/adjustment voltage associated with GR1 is applied through adjacent BL2/BL4 in figure 11 of Jung) is less than a voltage difference between the second voltage and a ground voltage (Jung teaches applying compensation voltages/dummy pulse voltage having magnitudes smaller than the write pulse voltage, [0046] of June, “…the amplitude of the dummy pulse may be less than that of the write pulse…”, Jung explicitly teaches applying reduced/intermediate dummy pulse or compensation voltages V1-V3 to adjacent cells instead of full write/ground differentials).
Regarding claim 7, the combination of Jung and Park teaches the memory device of claim 5, wherein: when the third voltage having a polarity opposite to the first voltage is applied to the first bit line following the first voltage, and the fourth voltage having a polarity opposite to the second voltage is applied to the first word line following the second voltage, in the first operation, a second adjustment voltage having a polarity opposite to the first adjustment voltage is applied to the second bit line (Park teaches sequential initialization operations using opposite polarities during successive initialization operations, see [0049]-[0052] of Park, [0061]-[0064] of Park, Park further teaches that initialization voltages V1 and V2 applied with opposite relative polarity relationships during different initialization condition, see figure 7 of Park. Jung teaches applying different compensation voltages to neighboring groups during subsequent operation, [0094]-[0101] of Jung, thus if opposite-polarity initialization operation are used (taught by Park), corresponding neighboring compensation voltages would also be adjusted depending on operation polarity and neighboring groups (taught by Park/Jung)).
Regarding claim 8, the combination of Jung and Park teaches the memory device of claim 1, wherein: an initialization operation is performed in a first direction from a memory cell among the plurality of memory cells of an address farthest in one side direction from a reference point where a voltage is applied to the first bit line toward the reference point (Park teaches sequential initialization operations progressing through memory cells connected along initialization paths, [0053] of Park, “…any memory cell in the first group connected to the first plate 20 or in the second group connected to the second plate 30 may be initialized in a serial manner…”, [0056] of Park, “..memory resistors of each resistive memory cell MC1 to MCn as successively connected to the initialization path may be initialized in turn…” Jung teaches direction/proximity-based neighboring-cell operations relative to a selected/reference cells, it would have been obvious to perform park’s sequential initialization operation in a direction progressing from the cells farther away from a voltage-application/reference point toward the reference point, as suggested by Jung’s distance-dependent compensation arrangement, in order to reduce voltage drop effects and improve initialization consistency across the array).
Regarding claim 9, the combination of Jung and Park teaches the memory device of claim 1, wherein: the plurality of memory cells is implemented with a plurality of memory layers, and with respect to the plurality of memory layers, an initialization operation is performed in a first direction from a lowest first layer to a highest second layer among the plurality of memory layers or in a second direction from the second layer to the first layer ([0089]-[0091] of Park, “…a three-dimensional memory device 600 includes a plurality of resistive memory devices 1-1 to 1-k formed on different layers…”)
Regarding claim 10, the combination of Jung and Park teaches the memory device of claim 1, wherein: in the second operation, the first voltage is a negative polarity voltage, the second voltage is a positive polarity voltage, the third voltage is a positive polarity voltage at a same level as the first voltage and the fourth voltage is a negative polarity voltage at a same level as the second voltage, and a positive polarity is the same as a polarity of a read voltage applied to a bit line among the plurality of bit lines or a word line among the plurality of word lines when reading a memory cell among the plurality of memory cells, and a negative polarity is opposite to the polarity of the read voltage (Park teaches opposite-polarity initialization operations, [0050] of Park, “initialization voltage V1 is greater than the second initialization voltage V2, a first initialization”, [0051] of Park, “second initialization voltage V2 is greater than the first initialization voltage V1, a second initialization”, Park further teaches SET and RESET operations performed with opposite current/voltage directions, suggesting complementary/opposite-polarity initialization operations. thus Park teaches first and second voltages have opposite polarity, and subsequent third/fourth voltages having opposite polarity relationship corresponding to subsequent initialization operations)
Regarding claim 11, the combination of Jung and Park teaches the memory device of claim 10, wherein: the first voltage is applied to the third bit line following the third voltage, and the second voltage is applied to the third word line following the fourth voltage (Park teaches sequential application of opposite polarity initialization voltages during successive initialization operations).
Regarding claim 12, the combination of Jung and Park teaches the memory device of claim 10, wherein: the third bit line is the same as the first bit line, and when an initialization operation is performed in a direction from a memory cell among the plurality of memory cells with an address farthest from a reference point where a voltage is applied to the first bit line to the reference point, a distance between the target memory cell and the reference point where the voltage is applied to the first bit line is closer than a distance between the next target memory cell and the reference point (Park teaches sequential initialization operations progressing along common initialization paths associated with common bit lines, Jung teaches grouping and compensating neighboring cells according to positional relationship and distance relative to the selected word lines. [0084] of Jung, “…the narrower (i.e., the shorter) the distance between the unselected memory cell and the selected memory cell MC22, the more the distribution of the unselected memory cell may droop, and thus, compensation for this is necessary…”, thus the combination teaches initialization progression relative to a reference location associated with the applied voltage line).
Regarding claim 13, the combination of Jung and Park teaches the memory device of claim 10, wherein: the third bit line is the same as the first bit line, and when an initialization operation is performed from one end of the first bit line to another end of the first bit line, the target memory cell is disposed in an area between the one end of the first bit line and a reference point based on the reference point where a voltage is applied to the first bit line, and the next target memory cell is disposed in an area between the other end of the first bit line and the reference point (Park teaches sequential initialization operations progressing along common initialization paths associated with common bit lines, Jung teaches spatially distributed neighboring groups located on opposite side of the selected memory cells along the same bit line or word line, figures 11-16 of Jung).
Regarding independent claim 14, it recites substantially the same limitations as claim 1, but in method form, claim 14 is thus rejected over Jung in view of Park for the same reason discussed for claim 1.
Regarding claim 15, the combination of Jung and Park teaches the initializing method of claim 14, wherein: applying the first adjustment voltage includes, when the target memory cell (MC33 in figure 11 of Jung) and the adjacent initialized memory cell (MC23, MC43 in figure 11 of Jung) share the first bit line (selected BL in figure 11 of Jung, e.g., BL3 in figure 11 of Jung), applying the first adjustment voltage (Jung teaches V1 is applied to GR1 in figure 12, [0115] of Jung, “…a first cell group GR1 may include adjacent memory cells MC23 and MC43 connected to the third bit line BL3, which is the same bit line connected to the selected memory cell MC33. Voltages across the memory cells in the first cell group GR1 may correspond to a first voltage V1…”, the differential across MC43 equals to V1) to the second word line (WL2 or WL4 in figure 11 of Jung) connected to the adjacent initialized memory cell (MC23 or MC43 in figure 11 of Jung).
Regarding claim 16, the combination of Jung and Park teaches the initializing method of claim 15, further comprising: applying a third voltage having a polarity opposite to the first voltage to the first bit line following the first voltage, and applying a fourth voltage having a polarity opposite to the second voltage to the first word line following the second voltage; and applying a different second adjustment voltage having a polarity opposite to the first adjustment voltage to the second word line (Park teaches sequential initialization operations using opposite polarities during successive initialization operations, see [0049]-[0052] of Park, [0061]-[0064] of Park, Park further teaches that initialization voltages V1 and V2 applied with opposite relative polarity relationships during different initialization condition, see figure 7 of Park. Jung teaches applying compensation voltages of opposite polarity to neighboring groups during subsequent operation, Jung [0105] teaches applying -2V to word lines WL1/WL3, teaches in [0106] applying 0V and different compensation levels to adjacent groups, Jung in figure 9A-9C teaches sequential dummy pulse operation DP1/DP2 having different timing/amplitude relationships. Jung teaches in [0097] using a third dummy pulse with smaller amplitude. Thus Jung teaches applying a different adjustment voltage having opposite polarity relative to another adjustment voltage during sequential operations affecting neighboring cells. Accordingly, it would have been obvious to modify Park’s sequential initialization operations using Jung’s opposite polarity neighboring compensation techniques to reduce disturbance effects and stabilize adjacent initialized memory cells).
Regarding claim 17, the combination of Jung and Park teaches the initializing method of claim 14, wherein: applying the first adjustment voltage includes, when the target memory cell (MC33 in figure 11 of Jung) and the adjacent initialized memory cell (MC32, MC34 in figure 11 of Jung) share the first word line (selected WL in figure 11 of Jung, e.g., WL3 in figure 11 of Jung), applying the first adjustment voltage (Jung teaches V1 is applied to GR1 in figure 12, [0110] of Jung, “…adjacent memory cells MC32 and MC34 connected to the third word line WL3, which is the same word line connected to the selected memory cell MC33…”) to the second bit line (BL2 or BL4 in figure 11 of Jung) connected to the adjacent initialized memory cell (MC32 or MC34 in figure 11 of Jung).
Regarding claim 18, the combination of Jung and Park teaches The initializing method of claim 17, further comprising: applying a third voltage having a polarity opposite to the first voltage to the first bit line following the first voltage, and applying a fourth voltage having a polarity opposite to the second voltage to the first word line following the second voltage; and applying a different second adjustment voltage having a polarity opposite to the first adjustment voltage to the second bit line (Park teaches sequential initialization operations using opposite polarities during successive initialization operations, see [0049]-[0052] of Park, [0061]-[0064] of Park, Park further teaches that initialization voltages V1 and V2 applied with opposite relative polarity relationships during different initialization condition, see figure 7 of Park. Jung teaches applying different compensation voltages to neighboring groups during subsequent operation, [0094]-[0101] of Jung, thus if opposite-polarity initialization operation are used (taught by Park), corresponding neighboring compensation voltages would also be adjusted depending on operation polarity and neighboring groups (taught by Park/Jung).
Regarding independent claim 19, it recites substantially the same limitation s claim 1, but in method form and with next-target-memory cell languish, claim 19 is thus rejected over Jung in view of Park for the same reason discussed for claim 1.
Regarding claim 20, the combination of Jung and Park teaches the initializing method of claim 19, wherein: the first voltage is a negative polarity voltage, the second voltage is a positive polarity voltage, the third voltage is a positive polarity voltage at a same level as the first voltage, and the fourth voltage is a negative polarity voltage at a same level as the second voltage, and a positive polarity is the same as a polarity of a read voltage applied to a bit line among the plurality of bit lines or a word line among the plurality of word lines when reading a memory cell among the plurality of memory cells, and a negative polarity is opposite to the polarity of the read voltage (Park teaches complementary SET/RESET initialization operations using opposite voltage/current direction, thus Park teaches first voltage of a first polarity, second voltage of opposite polarity, third/forth voltages corresponding to subsequent opposite-polarity initialization operations).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/ Primary Examiner, Art Unit 2824
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