DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 7/31/2026. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 10-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 2022/0173060) in view of Schmidberger (US 2015/0220433).
Re claim 10, Ahn teaches, under BRI, Figs. 1-3, 9A-B, 16 & 17, [0035, 0043, 0064, 0083, 0111], a semiconductor package, comprising:
-a package substrate (D3);
-a first semiconductor chip (D1) that includes a first peripheral circuit structure (PC1) and a first memory cell structure (in D1) on the first peripheral circuit structure (PC1) (Fig. 9B); and
-a second semiconductor chip (D2, D4) that includes a second peripheral circuit structure (PC2) and a second memory cell structure (in D2) on the second peripheral circuit structure (PC2) (Fig. 9B),
wherein the first memory cell structure (in D1) includes a single-level-cell memory cell array (e.g., each of the memory cells MC1 to MC8 may store one-bit data [0043]).
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Ahn does not explicitly teach wherein the second memory cell includes a multi-level-cell memory cell array.
Schmidberger teaches “SLC chips FC-SLC being allocated to a first area B1 and MLC chips FC-MLC being allocated to a second area B2” [0035].
As taught by Schmidberger, one of ordinary skill in the art would utilize & modify the above teaching to obtain the second memory cell including a multi-level-cell memory cell array as claimed, because it aids in achieving a maximum lifetime of the flash memory.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Schmidberger in combination Ahn due to above reason.
Re claim 11, Ahn teaches, Figs. 1 & 16, [0038, 0113], a controller (control logic 14 or controller 2002) that is configured to control the first memory cell structure (in D1) to be programmed in a single-level cell mode and the second memory cell structure (in D2) to be programmed in a multi-level cell mode.
Re claim 13, Ahn teaches, Fig. 9B, wherein the first peripheral circuit structure (PC1) includes a first driver circuit (e.g., transistor) that is configured to control the first memory cell structure, wherein the second peripheral circuit structure (PC2) includes a second driver circuit (e.g., transistor) that is configured to control the second memory cell structure, and wherein a structure of the first driver circuit is different from a structure of the second driver circuit (e.g., located at different level or based on number of considered transistors in each level).
Re claim 14, Ahn teaches, under BRI, Figs. 9B & 17, wherein a width of the first peripheral circuit structure (consider PC1 with 2100) in a first direction is greater than a width of the second peripheral circuit structure (PC2) in the first direction (x-axis), and wherein the first direction is parallel with a lower surface of the first peripheral circuit structure (PC1 with 2100).
Re claim 15, Ahn teaches, Figs. 9B & 17, wherein the first peripheral circuit structure (PC1 with 2100) includes a first substrate (2120) and a first driver circuit (e.g., transistor) on the first substrate, wherein the second peripheral circuit structure (PC2) includes a second substrate (under transistor) and a second driver circuit (e.g., transistor) on the second substrate, and wherein a width of the first substrate (2120) in the first direction (x-axis) is greater than a width of the second substrate (under transistor)in the first direction.
Re claim 16, Ahn teaches, Figs. 9B, 16 & 17, [0114-0115], wherein the first peripheral circuit structure (PC1) further includes a controller (2002) on the first substrate, wherein the controller (2002) is electrically connected to the first driver circuit and the second driver circuit (in chips 2200), wherein the controller (2002) does not overlap any of the first memory cell structure (in chip 2200), the second peripheral circuit structure, and the second memory cell structure (in chip 2200) in a second direction (vertical), and wherein the second direction is perpendicular to the lower surface of the first peripheral circuit structure (PC1).
Re claim 18, Ahn teaches, Figs. 9B & 17, a third semiconductor chip (over PC2) that includes a third peripheral circuit structure and a third memory cell structure on the third peripheral circuit structure (similar to structure in Fig. 9B), wherein the third memory cell structure includes a multi-level-cell memory cell array (e.g., each of the memory cells MC1 to MC8 may store one-bit data or two-or more-bit data, [0043]).
Allowable Subject Matter
3. Claims 1-9 are allowed. The allowable subject matter includes “a first semiconductor chip on the package substrate and having integrated therein a first peripheral circuit structure and a first memory cell structure on the first peripheral circuit structure…wherein the controller is electrically connected to and configured to control the first driver circuit and the second driver circuit” (claim 1); and
Claims 19-20 are allowed. The allowable subject matter includes “wherein the first peripheral circuit structure includes: a first lower peripheral dielectric layer…wherein the first memory cell structure includes…wherein the second peripheral circuit structure includes…wherein the second memory cell structure includes…and wherein the direction is perpendicular to a lower surface of the first lower peripheral dielectric layer” (claim 19).
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
5. The prior art(s) made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al. (US 2014/0006688) discloses mixed configuration of flash memory having MLC blocks and MLC as SLC blocks or combination; and Ke (US 2018/0373433) discloses flash memory module including first/second temporary blocks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/10/26
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