Prosecution Insights
Last updated: July 15, 2026
Application No. 18/624,904

NON-VOLATILE MEMORY

Non-Final OA §102§103
Filed
Apr 02, 2024
Priority
Jun 13, 2023 — RE 10-2023-0075710
Examiner
PHAM, LY D
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Non-Final)
94%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
970 granted / 1032 resolved
+26.0% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
23 currently pending
Career history
1046
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
34.1%
-5.9% vs TC avg
§102
36.5%
-3.5% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1032 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10, 11, 13, 14, 17 and 18 is/are rejected under 35 U.S.C. 103 as being obvious over Yuan et al. (US Pat Pub 2012/0314499) in view of Yun et al. (US Pat Pub 2019/0147964). The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Regarding claims 10, 11, 17 and 18, Yuan et al. disclose a storage device (for example figs. 1 – 18 and all related texts), comprising: a non-volatile memory device (for example fig. 3, comprising a memory cell block, fig. 5 and 6); and a storage controller (for example controller 244, fig. 3) configured to check a retention level of the memory cell block (para 0031 – 0033, retention level correlates to the number of program/erase cycles, and para 0035 discloses monitoring the number of Program/Erase cycles experienced by the memory), determine a read pass voltage based on the retention level (referred to in para 0035 as “the count of program/erase cycles and dynamically determine a current read pass voltage to use for the read process), and control the non-volatile memory device to apply the read pass voltage to the memory cell block (para 0035, “the read pass voltage optimized for cycled memory and …”). Yuan et al. disclose storage device as set forth above, except the retention level of the memory cell block is based on an off-cell count value of the memory cell block or a time period, wherein the time period is an amount of time that has elapsed since a program operation was performed on the memory cell block, or the time period is determined based on an internal temperature of the non-volatile memory device. The feature in which the retention level of the memory cell block is based on an off-cell count value of the memory cell block is taught by Yun et al. (see para 0171, 0172), and time period determined based on internal temperature of the non-volatile memory device (see para 0088). As with claims 11 and 18, Yun also discloses the storage controller configured to perform an off-cell count operation on the memory cell block to obtain the off-cell count value and check the retention level based on the off-cell count value (see para 0053 – 0055). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the references as cited, so to improve the operation efficiency of the memory device. Regarding claim 13, Yuan et al. also disclose the storage device of claim 10, wherein the storage controller is configured to check the retention level of the memory cell block after applying power to the non-volatile memory device (this limitation is considered inherent as the controller cannot perform any function without the memory cell block being applied with power). As per claim 14, Yuan et al. also disclose the storage device of claim 10, wherein the storage controller is configured to check a retention level of the memory cell block after performing a program operation on the memory cell block (para 0035: “… monitor the number of program/erase cycles experienced by the memory”. The number of cycles correlates to the retention level as explained above). Allowable Subject Matter Claims 12, 15, 16 and 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LY D. PHAM Examiner Art Unit 2827 /LY D PHAM/Primary Examiner, Art Unit 2827 April 3, 2026
Read full office action

Prosecution Timeline

Show 6 earlier events
Mar 26, 2026
Response Filed
Apr 08, 2026
Final Rejection mailed — §102, §103
May 11, 2026
Interview Requested
May 18, 2026
Applicant Interview (Telephonic)
May 23, 2026
Examiner Interview Summary
Jun 08, 2026
Response after Non-Final Action
Jul 08, 2026
Request for Continued Examination
Jul 13, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12676184
VOLTAGE REGULATOR, MEMORY DEVICE INCLUDING VOLTAGE REGULATOR, AND OPERATION METHOD OF MEMORY DEVICE
2y 9m to grant Granted Jul 07, 2026
Patent 12676200
SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINES
2y 0m to grant Granted Jul 07, 2026
Patent 12676198
ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
1y 11m to grant Granted Jul 07, 2026
Patent 12677408
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
1y 7m to grant Granted Jul 07, 2026
Patent 12670945
APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES
2y 2m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.3%)
1y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1032 resolved cases by this examiner. Grant probability derived from career allowance rate.

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