DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 7-20 in the reply filed on 08/28/2026 is acknowledged.
Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/28/2026.
Claim Objections
Claims 12-13 and 20 are objected to because of the following informalities:
Claim 12 (claim 20) recites “the respective line of semiconductor structure and the respective vertical-transistor channels in the respective column” which should be replaced with “a respective line of semiconductor structure and respective vertical-transistor channels in a respective column”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8, 11-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114530420 A to Hua et al. (hereinafter Hua) in view of Kim (US 2016/0104798).
With respect to claim 7, Hua discloses a semiconductor memory device (e.g., DRAM memory) (Hua, Figs. 34a-34d, Abstract, pp. 1-16), comprising:
trench isolations (e.g., isolation structure including a dielectric layer 105 between the bit lines 110) (Hua, Figs. 34b, 34d, pp. 14-15) arranged in a bit-line direction (e.g., y-direction);
gate structures (118) (Hua, Figs. 34a, 34d, pp. 14-15) arranged in a word-line direction (e.g., x-direction) perpendicular to the bit-line direction (e.g., y-direction);
an array of vertical-transistor channels (e.g., 101) (Hua, Figs. 34a, 34c, 34d, pp. 10, 14-15) arranged in a vertical direction (e.g., z-direction) perpendicular to the bit-line direction (e.g., y-direction) and the word-line direction (e.g., x-direction) and separated by the trench isolations (e.g., dielectric layer between the gates 118 of adjacent transistors 1001 and 1002) (Hua, Figs. 34a, 34c, 34d, pp. 10, 14-15) and gate structures (118), top ends of the array of the vertical-transistor channels (101) in each column being connected to a line (e.g., bit lines 110 including a semiconductor material) (Hua, Figs. 34a-34b, 34d, pp. 13-15) of semiconductor structure extending in the bit-line direction (e.g., y-direction) at a backside (e.g., the first surface is a back surface or a front surface) (Hua, Figs. 34a-34d, pp. 9, 14-15) of the semiconductor memory device (e.g., DRAM); and
gap tunnels (e.g., recesses 114) (Hua, Figs. 34a, 34c-34d, pp. 13-15) along the word-line direction (e.g., x-direction) that each crosses below the line (110) of semiconductor structure and between two neighboring vertical-transistor channels (e.g., the channel regions 101 of the adjacent vertical transistors 1001 and 1002) (Hua, Figs. 34a, 34c-34d, pp. 9-10, 13-15) in a first region (e.g., a region including the first recess 114) at the backside (e.g., the first surface) of the semiconductor memory device (e.g., DRAM).
Further, Hua does not specifically disclose air gap tunnels between two neighboring vertical-transistor channels.
However, Hua teaches forming the gap tunnels (e.g., cavities 114 and 115) between the gates (118) of two neighboring transistors (1001 and 1002) and adjacent bit lines to eliminate the coupling effect between adjacent gates (118) (Hua, Figs. 34a, 34c-34d, pp. 14-15) of two neighboring transistors and bit lines (110). Further, Kim teaches forming an air gap (170) (Kim, Figs. 1A, 1C, ¶0005, ¶0041) in the isolation film (e.g., 120, including oxide or nitride) between neighboring but lines (130) and semiconductor structures (e.g., active pillars 110 and body-tied structures 160) (Kim, Figs. 1A, 1C, ¶0128) to reduce parasitic capacitance between the adjacent conductive structures (e.g., 130 and 110/160).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua by forming the cavities between the gates of two neighboring transistors as air gaps in the isolation film as taught by Kim to have air gap tunnels between two neighboring vertical-transistor channels, in order to eliminate the coupling effect between adjacent gates of two neighboring vertical transistors; and to reduce parasitic capacitance between the adjacent conductive structures (Hua, pp. 14-15; Kim, ¶0005, ¶0041).
Regarding claim 8, Hua in view of Kim discloses the semiconductor memory device of claim 7. Further, Hua (in view of Kim) discloses the semiconductor memory device, wherein the air gap tunnels (114) (Hua, Figs. 34a, 34c-34d, pp. 13-15) are adjacent to the gate structures (e.g., 118).
Regarding claim 11, Hua in view of Kim discloses the semiconductor memory device of claim 7. Further, Hua (in view of Kim) discloses the semiconductor memory device, wherein a surface of at least one of the air gap tunnels (114) is covered by a spacer layer (106) (Hua, Figs. 34a, 34c-34d, pp. 11, 14-16) that surrounds an air gap (114).
Regarding claim 12, Hua in view of Kim discloses the semiconductor memory device of claim 7. Further, Hua (in view of Kim) discloses the semiconductor memory device, wherein top portions of the trench isolation (105) (Hua, Figs. 34c, 34d, pp. 13-16) at the backside of the semiconductor memory device are recessed (e.g., recesses to connect the second cavities 115 with the first cavities 114, as in Fig. 34c) to form gaps (e.g., the second cavities 115) above the trench isolation (e.g., isolation structure between the gates 118) and between bridge-shaped structures (bit lines 110 connected to the channels 101) (Hua, Figs. 34a-34b) each formed by the respective line of semiconductor structure (bit lines 110) and the respective vertical-transistor channels (101) in the respective column, and the gaps (115) are connected (e.g., the second cavities 115 are connected with the fist cavities 114) with the air gap tunnels (114), but does not specifically disclose air gaps, and the air gaps are connected with the air gap tunnels.
However, Hua teaches forming the gaps (e.g., cavities 115) between adjacent bit lines (110) to eliminate the coupling effect between the bit lines (110) (Hua, Figs. 34a, 34c-34d, pp. 14-15). Further, Kim teaches forming an air gap (170) (Kim, Figs. 1A, 1C, ¶0005, ¶0041) in the isolation film (120) including oxide or nitride would reduce parasitic capacitance between the adjacent conductive structures (e.g., buried bit lines).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua/Kim by forming the cavities between the bit lines as air gaps in the isolation film as taught by Kim to have the semiconductor memory device comprising air gaps, and the air gaps are connected with the air gap tunnels, in order to eliminate the coupling effect between adjacent bit lines; and to reduce parasitic capacitance between the adjacent bit lines (Hua, pp. 14-15; Kim, ¶0005, ¶0041).
Regarding claim 13, Hua in view of Kim discloses the semiconductor memory device of claim 12. Further, Hua (in view of Kim) discloses the semiconductor memory device, wherein a spacer layer (e.g., dielectric layer 105 surrounding the second cavities 115) (Hua, Figs. 34c, 34d, pp. 13-16) covers surfaces of the air gaps (115) between bridge-shaped structures each formed by the respective line of semiconductor structure (e.g., bit lines 110) and the respective vertical-transistor channels (101) in the respective column and the air gap tunnels (114) connected (e.g., each first cavity 114 is connected to the second cavity 115, as shown in Fig. 34c, thus the first cavities 114 are connected through the second cavity 115) with the air gap tunnels (114).
Regarding claim 14, Hua in view of Kim discloses the semiconductor memory device of claim 7. Further, Hua (in view of Kim) discloses the semiconductor memory device, wherein an insulation layer (106/105) covers a portion of the first region (e.g., the region including the first recesses 114) (Hua, Fig. 34a, pp. 14-16) and a second region (e.g., the region including the second recesses 115) (Hua, Fig. 34c) neighboring the portion of the first region (e.g., the region including the first recesses 114), and no air gap tunnel is formed within the second region.
With respect to claim 15, Hua discloses a semiconductor memory device (e.g., DRAM memory) (Hua, Figs. 34a-34d, Abstract, pp. 1-16), the semiconductor memory device comprising:
trench isolations (e.g., isolation structure including a dielectric layer 105 between the bit lines 110) (Hua, Figs. 34b, 34d, pp. 14-15) arranged in a bit-line direction (e.g., y-direction);
gate structures (118) (Hua, Figs. 34a, 34d, pp. 14-15) arranged in a word-line direction (e.g., x-direction) perpendicular to the bit-line direction (e.g., y-direction);
an array of vertical-transistor channels (e.g., 101) (Hua, Figs. 34a, 34c, 34d, pp. 10, 14-15) arranged in a vertical direction (e.g., z-direction) perpendicular to the bit-line direction (e.g., y-direction) and the word-line direction (e.g., x-direction) and separated by the trench isolations (e.g., dielectric layer between the gates 118 of adjacent transistors 1001 and 1002) (Hua, Figs. 34a, 34c, 34d, pp. 10, 14-15) and gate structures (118), top ends of the array of the vertical-transistor channels (101) in each column being connected to a line (e.g., bit lines 110 including a semiconductor material) (Hua, Figs. 34a-34b, 34d, pp. 13-15) of semiconductor structure extending in the bit-line direction (e.g., y-direction) at a backside (e.g., the first surface is a back surface or a front surface) (Hua, Figs. 34a-34d, pp. 9, 14-15) of the semiconductor memory device (e.g., DRAM); and
gap tunnels (e.g., recesses 114) (Hua, Figs. 34a, 34c-34d, pp. 13-15) along the word-line direction (e.g., x-direction) that each crosses below the line (110) of semiconductor structure and between two neighboring vertical-transistor channels (e.g., the channel regions 101 of the adjacent vertical transistors 1001 and 1002) (Hua, Figs. 34a, 34c-34d, pp. 9-10, 13-15) in a first region (e.g., a region including the first recesses 114) at the backside (e.g., the first surface) of the semiconductor memory device (e.g., DRAM).
Further, Hua does not specifically disclose (1) a memory system, comprising: a memory controller; and a semiconductor memory device coupled to the memory controller; (2) air gap tunnels between two neighboring vertical-transistor channels.
Regarding (1), Kim teaches forming a memory system (600), comprising: a memory controller (620) (Kim, Fig. 29, ¶0123-¶0130); and a semiconductor memory device (610) coupled to the memory controller (620), the semiconductor memory device (610) includes an air gap between neighboring but lines and active pillars to reduce parasitic capacitance between the adjacent bit lines and the active pillars, to improve electrical characteristics and performance of the electronic device.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua by forming an electronic device including a memory controller connected to a semiconductor memory device as taught by Kim to have a memory system, comprising: a memory controller; and a semiconductor memory device coupled to the memory controller, in order to provide a semiconductor memory device having reduced parasitic capacitance between the adjacent conductive structures to improve electrical characteristics and performance of the electronic device (Kim, ¶0005, ¶0041, ¶0123-¶0125, ¶0128, ¶0130).
Regarding (2), Hua teaches forming the gap tunnels (e.g., cavities 114 and 115) between the gates (118) of two neighboring transistors (1001 and 1002) and adjacent bit lines to eliminate the coupling effect between adjacent gates (118) (Hua, Figs. 34a, 34c-34d, pp. 14-15) of two neighboring transistors and bit lines (110). Further, Kim teaches forming an air gap (170) (Kim, Figs. 1A, 1C, ¶0005, ¶0041) in the isolation film (e.g., 120, including oxide or nitride) between neighboring but lines (130) and semiconductor structures (e.g., active pillars 110 and body-tied structures 160) (Kim, Figs. 1A, 1C, ¶0128) to reduce parasitic capacitance between the adjacent conductive structures (e.g., 130 and 110/160).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua by forming the cavities between the gates of two neighboring transistors as air gaps in the isolation film as taught by Kim to have air gap tunnels between two neighboring vertical-transistor channels, in order to eliminate the coupling effect between adjacent gates of two neighboring vertical transistors; and to reduce parasitic capacitance between the adjacent conductive structures (Hua, pp. 14-15; Kim, ¶0005, ¶0041).
Regarding claim 16, Hua in view of Kim discloses the memory system of claim 15. Further, Hua (in view of Kim) discloses the memory system, wherein the air gap tunnels (114) (Hua, Figs. 34a, 34c-34d, pp. 13-15) are adjacent to the gate structures (e.g., 118).
Regarding claim 19, Hua in view of Kim discloses the memory system of claim 15. Further, Hua (in view of Kim) discloses the memory system, wherein a surface of at least one of the air gap tunnels (114) is covered by a spacer layer (106) (Hua, Figs. 34a, 34c-34d, pp. 11, 14-16) that surrounds an air gap (114).
Regarding claim 20, Hua in view of Kim discloses the memory system of claim 15. Further, Hua (in view of Kim) discloses the memory system, wherein top portions of the trench isolation (105) (Hua, Figs. 34c, 34d, pp. 13-16) at the backside of the semiconductor memory device are recessed (e.g., recesses to connect the second cavities 115 with the first cavities 114, as in Fig. 34c) to form gaps (e.g., the second cavities 115) above the trench isolation (e.g., isolation structure between the gates 118) and between bridge-shaped structures (bit lines 110 connected to the channels 101) (Hua, Figs. 34a-34b) each formed by the respective line of semiconductor structure (bit lines 110) and the respective vertical-transistor channels (101) in the respective column, and the gaps (115) are connected (e.g., the second cavities 115 are connected with the fist cavities 114) with the air gap tunnels (114), wherein a spacer layer (e.g., dielectric layer 105 surrounding the second cavities 115) (Hua, Figs. 34c, 34d, pp. 13-16) covers surfaces of the gaps (115) between bridge-shaped structures each formed by the respective line of semiconductor structure (e.g., bit lines 110) and the respective vertical-transistor channels (101) in the respective column and the air gap tunnels (114) connected (e.g., each first cavity 114 is connected to the second cavity 115, as shown in Fig. 34c, thus the first cavities 114 are connected through the second cavity 115) with the air gap tunnels (114), but does not specifically disclose air gaps, and the air gaps are connected with the air gap tunnels.
However, Hua teaches forming the gaps (e.g., cavities 115) between adjacent bit lines (110) to eliminate the coupling effect between the bit lines (110) (Hua, Figs. 34a, 34c-34d, pp. 14-15). Further, Kim teaches forming an air gap (170) (Kim, Figs. 1A, 1C, ¶0005, ¶0041) in the isolation film (120) including oxide or nitride would reduce parasitic capacitance between the adjacent conductive structures (e.g., buried bit lines).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua/Kim by forming the cavities between the bit lines as air gaps in the isolation film as taught by Kim to have the semiconductor memory device comprising air gaps, and the air gaps are connected with the air gap tunnels, in order to eliminate the coupling effect between adjacent bit lines; and to reduce parasitic capacitance between the adjacent bit lines (Hua, pp. 14-15; Kim, ¶0005, ¶0041).
Claims 9-10 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114530420 A to Hua in view of Kim (US 2016/0104798) as applied to claim 7 (claim 15), and further in view of Sukekawa (US 2022/0059535) and Liu (US 2024/0040778).
Regarding claims 9 and 10, Hua in view of Kim discloses the semiconductor memory device of claim 7. Further, Hua does not specifically disclose the semiconductor memory device, further comprises metal shields between every two neighboring vertical-transistor channels along the word-line direction (as claimed in claim 9); wherein the air gap tunnels are adjacent to the metal shields (as claimed in claim 10).
However, Sukekawa teaches forming a semiconductor memory device (Sukekawa, Fig. 6A-6B, ¶0011-¶0037) comprising a vertical transistor and shield plates (12) (Sukekawa, Fig. 6A-6B, ¶0016, ¶0029) between every two neighboring vertical-transistor channels (6) (Sukekawa, Fig. 6A-6B, ¶0025-¶0029) along the word-line direction (e.g., x-direction), wherein the gaps (9) are adjacent to the shields (12), and the shields (12) are connected to a predetermined potential and functions as an isolation that electrically isolates the vertical transistor (33).
Further, Liu teaches forming metal shield (230) (Liu, Fig. 11B, ¶0111-¶0113, ¶0141, ¶0145) comprised of a material that is adaptively selected according to requirements in an actual manufacturing process, and includes a metal (e.g., tungsten) capable of shielding an electric field formed at the wordline structures (300).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Hua/Kim by forming shield plates in the gap between the channels of the vertical transistors as taught by Sukekaw, wherein the gap includes the air-gaps of Hua, and the shield plates include metal material as taught by Liu to have the semiconductor memory device, further comprises metal shields between every two neighboring vertical-transistor channels along the word-line direction (as claimed in claim 9); wherein the air gap tunnels are adjacent to the metal shields (as claimed in claim 10), in order to electrically isolate vertical transistors of the semiconductor memory device; and to provide a metal material capable of shielding an electric field formed at the wordline structures (Sukekawa, ¶0016, ¶0029; Liu, ¶0111, ¶0141, ¶0145).
Regarding claims 17 and 18, Hua in view of Kim discloses the memory system of claim 15. Further, Hua does not specifically disclose the memory system, further comprises metal shields between every two neighboring vertical-transistor channels along the word-line direction (as claimed in claim 17); wherein the air gap tunnels are adjacent to the metal shields (as claimed in claim 18).
However, Sukekawa teaches forming a semiconductor memory device (Sukekawa, Fig. 6A-6B, ¶0011-¶0037) comprising a vertical transistor and shield plates (12) (Sukekawa, Fig. 6A-6B, ¶0016, ¶0029) between every two neighboring vertical-transistor channels (6) (Sukekawa, Fig. 6A-6B, ¶0025-¶0029) along the word-line direction (e.g., x-direction), wherein the gaps (9) are adjacent to the shields (12), and the shields (12) are connected to a predetermined potential and functions as an isolation that electrically isolates the vertical transistor (33).
Further, Liu teaches forming metal shield (230) (Liu, Fig. 11B, ¶0111-¶0113, ¶0141, ¶0145) comprised of a material that is adaptively selected according to requirements in an actual manufacturing process, and includes a metal (e.g., tungsten) capable of shielding an electric field formed at the wordline structures (300).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory system of Hua/Kim by forming shield plates in the gap between the channels of the vertical transistors as taught by Sukekaw, wherein the gap includes the air-gaps of Hua, and the shield plates include metal material as taught by Liu to have the memory system, further comprises metal shields between every two neighboring vertical-transistor channels along the word-line direction (as claimed in claim 17); wherein the air gap tunnels are adjacent to the metal shields (as claimed in claim 18), in order to electrically isolate vertical transistors of the semiconductor memory device; and to provide a metal material capable of shielding an electric field formed at the wordline structures (Sukekawa, ¶0016, ¶0029; Liu, ¶0111, ¶0141, ¶0145).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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