DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, 9-14, 16, and 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura (US 2015 / 0221637).
As pertaining to Claim 1, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) a pixel (100; see Page 4 through Page 5, Para. [0088] and [0090]-[0092] and note that switches (111, 112, 113, 114, 115, 171) are transistors having a source electrode, a drain electrode, and a gate electrode) comprising (see Page 5 through Page 6, Para. [0106]-[0107]):
a first transistor (101) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (131) configured to receive first driving power (VDD; see (181)), a second electrode (i.e., a lower electrode), and a gate electrode connected to a first node (143; see Page 6, Para. [0108]);
a second transistor (111) connected between a data line (133) and the first node (143), and including a gate electrode electrically connected to a first scan line (see (161) in Fig. 18; see Page 6, Para. [0109]-[0110] and Page 13, Para. [0207]; and Page 14, Para. [0212]-[0213]);
a light emitting element (150; see Page 5, Para. [0101]) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (101), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (132) configured to receive second driving power (V3; see (182); see Page 6, Para. [0113] and Page 7, Para. [0127]);
a first capacitor (122) connected between the first node (143) and the first electrode (i.e., the upper electrode) of the light emitting element (150), the first capacitor (122) directly connected to the first node (143) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (150);
a second capacitor (123) connected between the first electrode (i.e., the upper electrode) of the light emitting element (150) and a third power line (see (135)) configured to receive first initialization power (V2); and
a third capacitor (121) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (143; see Page 8, Para. [0131]-[0132] and Page 11, Para. [0184]-[0189] and note that the second capacitor (123) is connected to third power line (135) to received voltage (V2); see Page 11, Para. [0187]; also see Page 13, Para. [0205] and Fig. 18 for an example implementation of switches (111, 112, 113, 114, 115, 171) as transistors; and see Page 14, Para. [0217] and Fig. 19 for an implementation of the driving circuits associated with the driving lines of Fig. 9).
As pertaining to Claim 3, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the second driving power (V3) is a voltage lower than the first driving power (VDD; see Page 6, Para. [0113] and Page 7, Para. [0127]).
As pertaining to Claim 4, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the first initialization power (V2) has a voltage value at which the light emitting element (150) is turned off in response to receiving the first initialization power (V2) at the first electrode (i.e., the upper electrode) of the light emitting element (150; see Page 7, Para. [0127]; Page 8, Para. [0131]-[0132]; and Page 11, Para. [0184]-[0189]).
As pertaining to Claim 5, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the first initialization power (V2) is ground power (again, see Page 7, Para. [0127]).
As pertaining to Claim 6, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) a third transistor (115) connected between the first electrode (i.e., the upper electrode) of the light emitting element (150) and the third power line (135), and including a gate electrode electrically connected to a second scan line (see (165) in Fig. 18; see Page 13 through Page 14, Para. [0211]-[0213]); and
a fourth transistor (112) including a first electrode (i.e., a lower electrode) electrically connected to a fourth power line (134), a second electrode (i.e., an upper electrode) connected to the first electrode (i.e., the lower electrode) of the third capacitor (121), and a gate electrode electrically connected to a third scan line (see (162) in Fig. 18; see Page 13, Para. [0208] and Page 14, Para. [0212]-[0213]).
As pertaining to Claim 9, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the third scan line (see (162) in Fig. 18) comprises a scan line identical to the second scan line (see (165) in Fig. 18; see Page 14, Para. [0213]).
As pertaining to Claim 10, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that a horizontal period (i.e., a scan period) comprises a first period (i.e., an arbitrary first scan period), a second period (i.e., an arbitrary second scan period), and a third period (i.e., an arbitrary third scan period), and wherein, during the first period (i.e., the arbitrary first scan period) and the second period (i.e., the arbitrary second scan period), a voltage of reference power (i.e., any arbitrary reference voltage of (Vsig) of (VsigH) or (VsigL)) is supplied to the data line (133), and during the third period (i.e., the arbitrary third scan period), a voltage of a data signal (i.e., any arbitrary voltage (Vsig)) is supplied to the data line (133; see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131] and [0135]).
As pertaining to Claim 11, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the reference power (i.e., any arbitrary reference voltage of (Vsig) of (VsigH) or (VsigL)) is a voltage value between the first driving power (VDD) and the second driving power (V3; again, see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131] and [0135]; and note that (V2) and/or (V3) may be a GND or VSS potential).
As pertaining to Claim 12, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that second initialization power (V1) is supplied to the fourth power line (134), and the reference power (i.e., any arbitrary reference voltage of (Vsig) of (VsigH) or (VsigL)) has a voltage that is equal to a voltage of the second initialization power (V1; again, see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131] and [0135]; and note that the reference power voltage can be (VsigL)).
As pertaining to Claim 13, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that during the first period (i.e., the arbitrary first scan period) the second transistor (111), the third transistor (115), and the fourth transistor (112) are turned on (see Fig. 4A, for example), and
during the second period (i.e., the arbitrary second scan period) and the third period (i.e., the arbitrary third scan period), the second transistor (111) is turned on (see Fig. 4B, for example), and the third transistor (115) and the fourth transistor (112) are turned off (see Fig. 4B with Fig. 5A; and note that the first, second, and third periods are arbitrarily defined periods; see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131], [0135], and [0138]; and Page 9, Para. [0147]).
As pertaining to Claim 14, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) a display device (see Page 1, Para. [0005]), comprising:
pixels (100; see Page 4 through Page 5, Para. [0088] and [0090]-[0092] and note that switches (111, 112, 113, 114, 115, 171) are transistors having a source electrode, a drain electrode, and a gate electrode) connected (see Fig. 18 in combination with Fig. 19) to first scan lines (161), second scan lines (165), third scan lines (162), and data lines (133),
wherein, among the pixels (100), a pixel (again, see any (100)) positioned on an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more) comprises (see Fig. 19 in combination with Fig. 9 and Fig. 18; also see Page 5 through Page 6, Para. [0106]-[0107]):
a first transistor (101) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (131) configured to receive first driving power (VDD; see (181)), a second electrode (i.e., a lower electrode), and a gate electrode connected to a first node (143; see Page 6, Para. [0108]);
a second transistor (111) connected between a j-th data line (133) and the first node (143), and configured to be turned on when a first scan signal (see (186A) and (161)) is supplied to an i-th first scan line (see (161) in Fig. 18; see Page 6, Para. [0109]-[0110] and Page 13, Para. [0207]; and Page 14, Para. [0212]-[0213]);
a light emitting element (150; see Page 5, Para. [0101]) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (101), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (132) configured to receive second driving power (V3; see (182); see Page 6, Para. [0113] and Page 7, Para. [0127]);
a first capacitor (122) connected between the first node (143) and the first electrode (i.e., the upper electrode) of the light emitting element (150), the first capacitor (122) directly connected to the first node (143) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (150);
a second capacitor (123) connected between the first electrode (i.e., the upper electrode) of the light emitting element (150) and a third power line (see (135)) configured to receive first initialization power (V2); and
a third capacitor (121) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (143; see Page 8, Para. [0131]-[0132] and Page 11, Para. [0184]-[0189]; and note that the second capacitor (123) is connected to third power line (135) to received voltage (V2); see Page 11, Para. [0187]; also see Page 13, Para. [0205] and Fig. 18 for an example implementation of switches (111, 112, 113, 114, 115, 171) as transistors; and see Page 14, Para. [0217] and Fig. 19 for an implementation of the driving circuits associated with the driving lines of Fig. 9).
As pertaining to Claim 16, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the pixel (again, see any (100)) positioned on the i-th pixel row (i is an integer of 0 or more) and the j-th pixel column (j is an integer of 0 or more) further comprises:
a third transistor (115) connected between the first electrode (i.e., the upper electrode) of the light emitting element (150) and the third power line (135), and configured to be turned on when a second scan signal (see (186E) and (165)) is supplied to an i-th second scan line (see (165) in Fig. 18; see Page 13 through Page 14, Para. [0211]-[0213]); and
a fourth transistor (112) including a first electrode (i.e., a lower electrode) electrically connected to a fourth power line (134) configured to receive second initialization power (V1), and a second electrode (i.e., an upper electrode) connected to the first electrode (i.e., the lower electrode) of the third capacitor (121), the fourth transistor (112) being configured to be turned on when a third scan signal (see (186B) and (162)) is supplied to an i-th third scan line (see (162) in Fig. 18; see Page 13, Para. [0208] and Page 14, Para. [0212]-[0213]).
As pertaining to Claim 18, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that a horizontal period (i.e., a scan period) in which the pixel (again, see any (100)) positioned on the i-th pixel row (i is an integer of 0 or more) and the j-th pixel column (j is an integer of 0 or more) is driven includes a first period (i.e., an arbitrary first scan period), a second period (i.e., an arbitrary second scan period), and a third period (i.e., an arbitrary third scan period), the display device further comprising:
a data driver (183) configured to supply a voltage of reference power (i.e., any arbitrary reference voltage of (Vsig) of (VsigH) or (VsigL)) to the j-th data line (133) during the first period (i.e., the arbitrary first scan period) and the second period (i.e., the arbitrary second scan period), and supply a voltage of a data signal (i.e., any arbitrary voltage (Vsig)) to the j-th data line (133) during the third period (i.e., the arbitrary third scan period; see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131] and [0135]);
a first scan driver (186A) configured to supply the first scan signal (see (186A) and (161)) to the i-th first scan line (161) during the first to the third periods (i.e., the arbitrary first scan period to the arbitrary third scan period; see Page 6, Para. [0109]-[0110] and Page 13, Para. [0207]; and Page 14, Para. [0212]-[0213]);
a second scan driver (186E) configured to supply the second scan signal (see (186E) and (165)) to the i-th second scan line (165) during the first period (i.e., the arbitrary first scan period; see Page 13 through Page 14, Para. [0211]-[0213]); and
a third scan driver (186B) configured to supply the third scan signal (see (186B) and (162)) to the i-th third scan line (162) during the first period (i.e., the arbitrary first scan period; see Page 13, Para. [0208] and Page 14, Para. [0212]-[0213]; and note that the first, second, and third periods are arbitrarily defined periods; also see Page 8, Para. [0131], [0135], and [0138]; and Page 9, Para. [0147]).
As pertaining to Claim 19, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the reference power (i.e., any arbitrary reference voltage of (Vsig) of (VsigH) or (VsigL)) is equal to the second initialization power (V1) having a voltage between the first driving power (VDD) and the second driving power (V3; see Page 6, Para. [0109]-[0110]; Page 7, Para. [0125]-[0127], and [0129]; also see Page 8, Para. [0131] and [0135]; and note that (V2) and/or (V3) may be a GND or VSS potential).
As pertaining to Claim 20, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that the third scan line (see (162) in Fig. 18) is a scan line identical to the second scan line (see (165) in Fig. 18; see Page 14, Para. [0213]), and the third scan driver (186B) is a driver identical to the second scan driver (186E; see Page 14, Para. [0212]).
As pertaining to Claim 21, Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) an electronic device (see Page 1, Para. [0005]), comprising:
a display device including pixels (100; see Page 4 through Page 5, Para. [0088] and [0090]-[0092] and note that switches (111, 112, 113, 114, 115, 171) are transistors having a source electrode, a drain electrode, and a gate electrode) connected (see Fig. 18 in combination with Fig. 19) to first scan lines (161), second scan lines (165), third scan lines (162), and data lines (133; see Page 5 through Page 6, Para. [0106]-[0107]); and
a host (see (301) in Fig. 19) providing input image data (i.e., a video signal) to the display device (see Page 6, Para. [0109] and Page 14, Para. [0217]),
wherein each of the pixels (100) comprises:
a first transistor (101) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (131) configured to receive first driving power (VDD; see (181)), a second electrode (i.e., a lower electrode), and a gate electrode connected to a first node (143; see Page 6, Para. [0108]);
a second transistor (111) connected between a j-th data line (133) and the first node (143), and configured to be turned on when a first scan signal (see (186A) and (161)) is supplied to an i-th first scan line (see (161) in Fig. 18; see Page 6, Para. [0109]-[0110] and Page 13, Para. [0207]; and Page 14, Para. [0212]-[0213]);
a light emitting element (150; see Page 5, Para. [0101]) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (101), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (132) configured to receive second driving power (V3; see (182); see Page 6, Para. [0113] and Page 7, Para. [0127]);
a first capacitor (122) connected between the first node (143) and the first electrode (i.e., the upper electrode) of the light emitting element (150), the first capacitor (122) directly connected to the first node (143) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (150);
a second capacitor (123) connected between the first electrode (i.e., the upper electrode) of the light emitting element (150) and a third power line (see (135)) configured to receive first initialization power (V2); and
a third capacitor (121) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (143; see Page 8, Para. [0131]-[0132] and Page 11, Para. [0184]-[0189]; and note that the second capacitor (123) is connected to third power line (135) to received voltage (V2); see Page 11, Para. [0187]; also see Page 13, Para. [0205] and Fig. 18 for an example implementation of switches (111, 112, 113, 114, 115, 171) as transistors; and see Page 14, Para. [0217] and Fig. 19 for an implementation of the driving circuits associated with the driving lines of Fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura.
As pertaining to Claim 2, Kimura does not explicitly state that a ratio of a capacitance of the second capacitor (123) to a capacitance of the first capacitor (122) is at least 0.1.
However, Kimura does explicitly disclose (again, see Fig. 9 in combination with Fig. 18 and Fig. 19) that the capacitance of the second capacitor (123) is arbitrarily adjusted relative to the capacitance of the first capacitor (122) to control a desired change in voltage at first transistor (101; see Page 11, Para. [0187]). That is, Kimura expressly discloses that there were design incentives, namely the control of a desired change in voltage at the first transistor (101), that would have prompted adaptation of the disclosed pixel (100) to include a first capacitor (122) and a second capacitor (123) having a ratio of a capacitance of the second capacitor (123) to a capacitance of the first capacitor (122) that is at least 0.1, as this ratio of capacitance would have been encompassed in the known variations, principles, and/or design scope suggested by Kimura to produce the desired and predictable change in voltage at the first transistor (101) that is suggested by Kimura.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a ratio of a capacitance of the second capacitor (123) to a capacitance of the first capacitor (122) is at least 0.1 in order to control of a desired change in voltage at the first transistor (101) in the manner suggested by Kimura.
Claims 7-8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Miura et al. (hereinafter “Miura” US 2019 / 0197957).
As pertaining to Claim 7, while Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that each of the first (101), second (111), third (115), and fourth transistors (112) comprises a metal-oxide-semiconductor field-effect transistor (MOSFET; see Page 4, Para. [0090]-[0091] and Page 10 through Page 11, Para. [0177]), and that the MOSFET transistors can include multi-gate structures (again, see Page 4, Para. [0091]), Kimura does not explicitly show an embodiment in which each of the first, second, third, and fourth transistors includes a body electrode.
However, in the same field of endeavor, Miura discloses (see Fig. 2) a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform (see Page 1, Para. [0004] and [0006]-[0007]) by incorporating a pixel circuit (20) that comprises all metal-oxide-semiconductor field-effect transistors (MOSFETs; see Page 2, Para. [0046]) that each include a body electrode connected to a first driving power (Vccp; see Page 3, Para. [0061]-[0063]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimura and Miura, such that each of the first (101), second (111), third (115), and fourth transistors (112) disclosed by Kimura comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) including a body electrode connected to the first driving power (see (Vccp) of Miura corresponding to (VDD) of Kimura), in order to provide a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform, as suggested by Miura.
As pertaining to Claim 8, Miura discloses (see Fig. 2) that a the first driving power (see (Vccp) of Miura corresponding to (VDD) of Kimura) is supplied to the body electrode of each of the first (101), second (111), third (115), and fourth transistors (112; see Page 3, Para. [0061]-[0063]).
As pertaining to Claim 17, while Kimura discloses (see Fig. 9 in combination with Fig. 18 and Fig. 19) that each of the first (101), second (111), third (115), and fourth transistors (112) comprises a metal-oxide-semiconductor field-effect transistor (MOSFET; see Page 4, Para. [0090]-[0091] and Page 10 through Page 11, Para. [0177]), and that the MOSFET transistors can include multi-gate structures (again, see Page 4, Para. [0091]), Kimura does not explicitly show an embodiment in which each of the first, second, third, and fourth transistors includes a body electrode, wherein the first driving power is supplied to the body electrode of each of the first, second, third, and fourth transistors.
However, in the same field of endeavor, Miura discloses (see Fig. 2) a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform (see Page 1, Para. [0004] and [0006]-[0007]) by incorporating a pixel circuit (20) that comprises all metal-oxide-semiconductor field-effect transistors (MOSFETs; see Page 2, Para. [0046]) that each include a body electrode connected to a first driving power (Vccp; see Page 3, Para. [0061]-[0063]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimura and Miura, such that each of the first (101), second (111), third (115), and fourth transistors (112) disclosed by Kimura comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) including a body electrode that is supplied with the first driving power (see (Vccp) of Miura corresponding to (VDD) of Kimura), in order to provide a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform, as suggested by Miura.
Response to Arguments
Applicant's arguments filed 26 November 2025 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, particularly Kimura and Zhang, teach or fairly suggest a first node in combination with first, second, and third capacitors with “the first capacitor directly connected to the first node and directly connected to the first electrode of the light emitting element” (see Remarks at Pages 8 through 10). With respect to the teachings of Zhang, the examiner agrees. However, with respect to the teachings of Kimura, the examiner respectfully disagrees.
In fact, Kimura plainly discloses (see Fig. 9) the claimed pixel circuit of at least independent Claims 1, 14, and 21, including a first node (143) and first, second and third capacitors (122, 123, 121), wherein the first capacitor (122) is connected between the first node (143) and the first electrode (i.e., the upper electrode) of the light emitting element (150), the first capacitor (122) directly connected to the first node (143) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (150).
For at least these reasons, the rejection of Claims 1-14 and 16-21 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Heganovic et al. (US 11,069,292) at Figure 9; Koide et al. (US 2023 / 0017957) at Figure 3; Yoon et al. (US 9,953,583) at Figure 3; and Koyama (US 9,030,105) at Figure 1A all disclose pixel circuit structures that are relevant to the pixel circuit structure disclosed by the applicant.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623