DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28 April 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-14, 16, and 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toyotaka et al. (hereinafter “Toyotaka” US 2020 / 0320930).
As pertaining to Claim 1, Toyotaka discloses (see Fig. 7B) a pixel (PIX) comprising:
a first transistor (Tr3) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (AL) configured to receive first driving power (i.e., high driving power (AL)), a second electrode (i.e., a lower electrode), and a gate electrode directly connected to a first node (ND2);
a second transistor (Tr2) connected between a data line (WDL) and the first node (ND2), and including a gate electrode electrically connected to a first scan line (GL2);
a light emitting element (LD) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (Tr3), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (CAT) configured to receive second driving power (i.e., low driving power (CAT));
a first capacitor (C2) connected between the first node (ND2) and the first electrode (i.e., the upper electrode) of the light emitting element (LD), the first capacitor (C2) directly connected to the first node (ND2) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (LD);
a second capacitor (C3) connected between the first electrode (i.e., the upper electrode) of the light emitting element (LD) and a third power line (VL) configured to receive first initialization power (i.e., initialization power (VL)); and
a third capacitor (C1) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (ND2; see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 3, Toyotaka discloses (see Fig. 7B) that the second driving power (CAT) is a voltage lower than the first driving power (AL; see Page 24, Para. [0361] for example values of (CAT) and (AL)).
As pertaining to Claim 4, Toyotaka discloses (see Fig. 7B) that the first initialization power (VL) has a voltage value at which the light emitting element (LD) is turned off in response to receiving the first initialization power (VL) at the first electrode (i.e., the upper electrode) of the light emitting element (LD; see Page 24, Para. [0361] for an example value of (VL); also see Fig. 8 and note that (LD) is turned off from (T1) through (T6) including when (VL) is received at the first electrode of (LD); and see Page 11 through Page 12, Para. [0153]-[0170]).
As pertaining to Claim 5, Toyotaka discloses (see Fig. 7B) that the first initialization power (VL) is a ground power (i.e., an arbitrary low power; again, see Page 24, Para. [0361] for an example value of (VL)).
As pertaining to Claim 6, Toyotaka discloses (see Fig. 7B) a third transistor (Tr4) connected between the first electrode (i.e., the upper electrode) of the light emitting element (LD) and the third power line (VL), and including a gate electrode electrically connected to a second scan line (GL1); and
a fourth transistor (Tr1) including a first electrode (i.e., a left electrode) electrically connected to a fourth power line (DL), a second electrode (i.e., a right electrode) connected to the first electrode (i.e., the upper electrode) of the third capacitor (C1), and a gate electrode electrically connected to a third scan line (GL1; again, see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 7, Toyotaka discloses (see Fig. 7B) that each of the first, second, third, and fourth transistors (Tr3, Tr2, Tr4, Tr1) comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) including a body electrode (see Page 4, Para. [0064]; Page 7 through Page 8, Para. [0112]; and Fig. 6B, for example, with Page 9, Para. [0133] and note that all of (Tr3, Tr2, Tr4, Tr1) can be implemented with a MOSFET including a body electrode in the manner of the embodiment of Fig. 6B).
As pertaining to Claim 9, Toyotaka discloses (see Fig. 7B) that the third scan line (GL1) comprises a scan line identical to the second scan line (GL1; again, see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 10, Toyotaka discloses (see Fig. 7B along with Fig. 8) that a horizontal period (i.e., a scan period) comprises a first period (i.e., an arbitrary first scan period), a second period (i.e., an arbitrary second scan period), and a third period (i.e., an arbitrary third scan period), and
wherein, during the first period (i.e., the arbitrary first scan period) and the second period (i.e., the arbitrary second scan period), a voltage of reference power (i.e., any arbitrary reference voltage from (VGND) or (V1) to (VW) to (VDATA)) is supplied to the data line (WDL; see Fig. 8), and during the third period (i.e., the arbitrary third scan period), a voltage of a data signal (VW) is supplied to the data line (WDL; see Page 11 through Page 12, Para. [0153]-[0170]; and see Page 15, Para. [0217]).
As pertaining to Claim 11, Toyotaka discloses (see Fig. 7B along with Fig. 8) that the reference power (i.e., any arbitrary reference voltage from (VGND) or (V1) to (VW) to (VDATA)) is a voltage value between the first driving power (AL) and the second driving power (CAT; see Page 24, Para. [0361] and note that (WDL) varies between the (CAT) voltage and the high voltage (AL)).
As pertaining to Claim 12, Toyotaka discloses (see Fig. 7B along with Fig. 8) that second initialization power (i.e., any arbitrary voltage between (VGND) and (VDATA)) is supplied to the fourth power line (DL), and the reference power (i.e., any arbitrary reference voltage from (VGND) or (V1) to (VW) to (VDATA)) has a voltage that is equal to a voltage of the second initialization power (i.e., any arbitrary voltage between (VGND) and (VDATA); again, see Page 11 through Page 12, Para. [0153]-[0170]; and see Page 15, Para. [0217]).
As pertaining to Claim 13, Toyotaka discloses (see Fig. 7B along with Fig. 8) that during the first period (i.e., the arbitrary first scan period) the second transistor (Tr2), the third transistor (Tr4), and the fourth transistor (Tr1) are turned on (see Fig. 8 when (GL1) and (GL2) are high level), and
during the second period (i.e., the arbitrary second scan period) and the third period (i.e., the arbitrary third scan period), the second transistor (Tr2) is turned on (see Fig. 8 when (GL2) is high level), and the third transistor (Tr4) and the fourth transistor (Tr1) are turned off (see Fig. 8 when (GL1) is low level; and note that the first, second, and third periods are arbitrarily defined periods and can include any arbitrary portions of (T1) through (T7) in Fig. 8; see Page 11 through Page 12, Para. [0153]-[0170]).
As pertaining to Claim 14, Toyotaka discloses (see Fig. 5B with Fig. 7B) a display device (DD), comprising:
pixels (PIX) connected to first scan lines (GL2), second scan lines (GL1), third scan lines (again, see (GL1)), and data lines (WDL; see Page 8 through Page 9, Para. [0123]-[0124]),
wherein, among the pixels (PIX), a pixel (again, see any (PIX)) positioned on an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more) comprises (see Fig. 7B):
a first transistor (Tr3) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (AL) configured to receive first driving power (i.e., high driving power (AL)), a second electrode (i.e., a lower electrode), and a gate electrode directly connected to a first node (ND2);
a second transistor (Tr2) connected between a j-th data line (WDL) and the first node (ND2), and configured to be turned on when a first scan signal (i.e., a signal on (GL2)) is supplied to an i-th first scan line (GL2);
a light emitting element (LD) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (Tr3), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (CAT) configured to receive second driving power (i.e., low driving power (CAT));
a first capacitor (C2) connected between the first node (ND2) and the first electrode (i.e., the upper electrode) of the light emitting element (LD), the first capacitor (C2) directly connected to the first node (ND2) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (LD);
a second capacitor (C3) connected between the first electrode (i.e., the upper electrode) of the light emitting element (LD) and a third power line (VL) configured to receive first initialization power (i.e., initialization power (VL)); and
a third capacitor (C1) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (ND2; see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 16, Toyotaka discloses (see Fig. 7B and Fig. 8) that the pixel (PIX) positioned on the i-th pixel row and the j-th pixel column further comprises (see Fig. 7B):
a third transistor (Tr4) connected between the first electrode (i.e., the upper electrode) of the light emitting element (LD) and the third power line (VL), and configured to be turned on when a second scan signal (i.e., a signal on (GL1)) is supplied to an i-th second scan line (GL1); and
a fourth transistor (Tr1) including a first electrode (i.e., a left electrode) electrically connected to a fourth power line (DL) configured to receive second initialization power (DL), and a second electrode (i.e., a right electrode) connected to the first electrode (i.e., the upper electrode) of the third capacitor (C1), the fourth transistor (Tr1) being configured to be turned on when a third scan signal (i.e., a signal on (GL1)) is supplied to an i-th third scan line (GL1; again, see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 18, Toyotaka discloses (see Fig. 5B and Fig. 7B along with Fig. 8) that a horizontal period (i.e., a scan period) in which the pixel (PIX) positioned on the i-th pixel row and the j-th pixel column is driven includes a first period (i.e., an arbitrary first scan period), a second period (i.e., an arbitrary second scan period), and a third period (i.e., an arbitrary third scan period), the display device (DD) further comprising:
a data driver (i.e., see (SD) in Fig. 5B; see Page 6, Para. [0098]; and Page 8 through Page 9, Para. [0124]) configured to supply a voltage of reference power (i.e., any arbitrary reference voltage from (VGND) or (V1) to (VW) to (VDATA)) to the j-th data line (WDL; see Fig. 8) during the first period (i.e., the arbitrary first scan period) and the second period (i.e., the arbitrary second scan period), and supply a voltage of a data signal (VW) to the j-th data line (WDL) during the third period (i.e., the arbitrary third scan period);
a first scan driver (i.e., the portion of (GD) generating (GL2); see Page 5, Para. [0080]-[0081]) configured to supply the first scan signal (i.e., the signal on (GL2)) to the i-th first scan line (GL2) during the first to third periods (i.e., the arbitrary first, second, and third scan periods);
a second scan driver (i.e., the portion of (GD) generating (GL1)) configured to supply the second scan signal (i.e., the signal on (GL1)) to the i-th second scan line (GL1) during the first period (i.e., the arbitrary first scan period); and
a third scan driver (i.e., the portion of (GD) generating (GL1)) configured to supply the third scan signal (i.e., the signal on (GL1)) to the i-th third scan line (GL1) during the first period (i.e., the arbitrary first scan period; see Page 11 through Page 12, Para. [0153]-[0170]; and see Page 15, Para. [0217]; and note that the first, second, and third periods are arbitrarily defined periods and can include any arbitrary portions of (T1) through (T7) in Fig. 8).
As pertaining to Claim 19, Toyotaka discloses (see Fig. 7B along with Fig. 8) that the reference power (i.e., any arbitrary reference voltage from (VGND) or (V1) to (VW) to (VDATA)) is equal to the second initialization power (i.e., any arbitrary voltage between (VGND) and (VDATA)) having a voltage between the first driving power (AL) and the second driving power (CAT; see Page 24, Para. [0361] and note that (WDL) and (DL) vary between the (CAT) voltage and the high voltage (AL); and see Page 11 through Page 12, Para. [0153]-[0170]; and Page 15, Para. [0217]).
As pertaining to Claim 20, Toyotaka discloses (see Fig. 7B) that the third scan line (GL1) is a scan line identical to the second scan line (GL1), and the third scan driver (i.e., the portion of (GD) generating (GL1)) is a driver identical to the second scan driver (i.e., the portion of (GD) generating (GL1); again, see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
As pertaining to Claim 21, Toyotaka discloses (see Fig. 5B with Fig. 7B) an electronic device (see Page 1, Para. [0001]), comprising:
a display device (DD) including pixels (PIX) connected to first scan lines (GL2), second scan lines (GL1), third scan lines (again, see (GL1)), and data lines (WDL; see Page 8 through Page 9, Para. [0123]-[0124]); and
a host (SD, GD) providing input image data to the display device (DD; see Page 6, Para. [0098]; Page 8 through Page 9, Para. [0124]; and Page 5, Para. [0080]-[0081]),
wherein each of the pixels (PIX) comprises (see Fig. 7B):
a first transistor (Tr3) including a first electrode (i.e., an upper electrode) electrically connected to a first power line (AL) configured to receive first driving power (i.e., high driving power (AL)), a second electrode (i.e., a lower electrode), and a gate electrode directly connected to a first node (ND2);
a second transistor (Tr2) connected to a j-th data line (WDL) and directly connected to the first node (ND2), and configured to be turned on when a first scan signal (i.e., a signal on (GL2)) is supplied to an i-th first scan line (GL2);
a light emitting element (LD) including a first electrode (i.e., an upper electrode) connected to the second electrode (i.e., the lower electrode) of the first transistor (Tr3), and a second electrode (i.e., a lower electrode) electrically connected to a second power line (CAT) configured to receive second driving power (i.e., low driving power (CAT));
a first capacitor (C2) connected between the first node (ND2) and the first electrode (i.e., the upper electrode) of the light emitting element (LD), the first capacitor (C2) directly connected to the first node (ND2) and directly connected to the first electrode (i.e., the upper electrode) of the light emitting element (LD);
a second capacitor (C3) connected between the first electrode (i.e., the upper electrode) of the light emitting element (LD) and a third power line (VL) configured to receive first initialization power (i.e., initialization power (VL)); and
a third capacitor (C1) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to the first node (ND2; see Page 9 through Page 10, Para. [0140]-[0141] in combination with Page 9, Para. [0125]-[0133]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka.
As pertaining to Claim 2, Toyotaka does not explicitly state that a ratio of a capacitance of the second capacitor (C3) to a capacitance of the first capacitor (C2) is at least 0.1.
However, Toyotaka does explicitly disclose that the capacitance of the second capacitor (C3) can be adjusted relative to the capacitance of the first capacitor (C2) in consideration of leakage current or the like of a transistor provided in the pixel portion so that charge can be held for a predetermined period (see Page 17, Para. [0253]). That is, Toyotaka expressly discloses that there were design incentives, namely the consideration of leakage current or the like of a transistor provided in the pixel portion so that charge can be held for a predetermined period, that would have prompted adaptation of the disclosed pixel (PIX) to include a first capacitor (C2) and a second capacitor (C3) having a ratio of a capacitance of the second capacitor (C3) to a capacitance of the first capacitor (C2) that is at least 0.1, as this ratio of capacitance would have been encompassed in the known variations, principles, and/or design scope suggested by Toyotaka to produce the desired and predictable consideration of leakage current or the like of a transistor provided in the pixel portion so that charge can be held for a predetermined period, as suggested by Toyotaka.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a ratio of a capacitance of the second capacitor (C3) to a capacitance of the first capacitor (C2) is at least 0.1 in consideration of leakage current or the like of a transistor provided in the pixel portion so that charge can be held for a predetermined period in the manner suggested by Toyotaka.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka in view of Miura et al. (hereinafter “Miura” US 2019 / 0197957).
As pertaining to Claim 8, Toyotaka does not explicitly disclose that the first driving power is supplied to the body electrode of each of the first, second, third, and fourth transistors.
However, in the same field of endeavor, Miura discloses (see Fig. 2) a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform (see Page 1, Para. [0004] and [0006]-[0007]) by incorporating a pixel circuit (20) that comprises all metal-oxide-semiconductor field-effect transistors (MOSFETs; see Page 2, Para. [0046]) that each include a body electrode connected to and supplied with a first driving power (Vccp; see Page 3, Para. [0061]-[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Toyotaka with the teachings of Miura, such that the first driving power is supplied to the body electrode of each of the first, second, third, and fourth transistors of Toyotaka, as suggested by Miura, in order to provide a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform.
As pertaining to Claim 17, Toyotaka discloses (see Fig. 7B) that each of the first, second, third, and fourth transistors (Tr3, Tr2, Tr4, Tr1) comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) including a body electrode (see Page 4, Para. [0064]; Page 7 through Page 8, Para. [0112]; and Fig. 6B, for example, with Page 9, Para. [0133] and note that all of (Tr3, Tr2, Tr4, Tr1) can be implemented with a MOSFET including a body electrode in the manner of the embodiment of Fig. 6B).
Toyotaka does not explicitly disclose that the first driving power is supplied to the body electrode of each of the first, second, third, and fourth transistors.
However, in the same field of endeavor, Miura discloses (see Fig. 2) a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform (see Page 1, Para. [0004] and [0006]-[0007]) by incorporating a pixel circuit (20) that comprises all metal-oxide-semiconductor field-effect transistors (MOSFETs; see Page 2, Para. [0046]) that each include a body electrode connected to and supplied with a first driving power (Vccp; see Page 3, Para. [0061]-[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Toyotaka with the teachings of Miura, such that the first driving power is supplied to the body electrode of each of the first, second, third, and fourth transistors of Toyotaka, as suggested by Miura, in order to provide a pixel circuit structure in which display unevenness is suppressed, display quality is improved, and transistor characteristics are made uniform.
Response to Arguments
Applicant’s arguments with respect to Claims 1-14 and 16-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, particularly Kimura, teach or fairly suggest a pixel circuit structure having the newly claimed “first node” having the “direct” connections as newly recited (see Remarks at Pages 7 through 10). Respectfully, the applicant’s argument is moot in view of at least the teachings of Toyotaka as newly relied upon by the examiner in the above rejections.
For at least the reasons provided above, the rejection of Claims 1-14 and 16-21 is maintained.
In order to further prosecution in the application, the examiner respectfully points out that the prior art is replete with references that read on the claimed invention. In addition to the newly relied upon teachings of Toyotaka, the examiner respectfully directs attention to the references to Jeong et al. (US 11,756,480) at Figure 13, Heganovic et al. (US 11,069,292), previously cited by the examiner, at Figure 9, and Takahashi et al. (US 11,508,307) at Figure 1. All of these cited references disclose the features of at least the independent Claims 1, 14, and 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Koide et al. (US 2023 / 0017957) at Figure 3; Yoon et al. (US 9,953,583) at Figure 3; and Koyama (US 9,030,105) at Figure 1A all disclose pixel circuit structures that are relevant to the pixel circuit structure disclosed by the applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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