Prosecution Insights
Last updated: October 01, 2026
Application No. 18/625,205

SEMICONDUCTOR DEVICE

Final Rejection §112
Filed
Apr 03, 2024
Priority
Nov 20, 2023 — RE 10-2023-0160312
Examiner
HEISTERKAMP, JUSTIN BRYCE
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
3 (Final)
99%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 99% — above average
99%
Career Allowance Rate
81 granted / 82 resolved
+30.8% vs TC avg
Minimal +2% lift
Without
With
+2.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
13 currently pending
Career history
96
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
27.0%
-13.0% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
32.2%
-7.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 82 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-32 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation, “a synchronization path coupled to the at least one merge node and suitable for outputting . . . a corresponding signal of the first and second data signals as the data signal synchronized with at least one data strobe signal.” It is unclear how the synchronization path may output a corresponding signal that is the data signal that is also provided to the first and second data paths. That is, according to FIG. 1, the first and second data path receive the data signal DQ and the synchronization path outputs the internal data signals Dqi, DQq, DQib, and DQqb (see annotated FIG. 1 below). The applicant is advised to amend “the data signal” in the limitation above to either read as “an internal data signal” or provide a unique designator to distinctly identify the output of the synchronization path from the input of the first and second data paths. Alternatively, the applicant may amend claim 1 to read as, “a synchronization path coupled to the at least one merge node and suitable for outputting, in one of the first and second modes, an internal data signal [[a]] corresponding to one of the first data and second data signals synchronized with at least one data strobe signal. PNG media_image1.png 440 770 media_image1.png Greyscale Figure 1 (annotated) Claims 2-13 are rejected because they depend on claim 1; and therefore, contain at least the same defect(s). Claim 8 is rejected because it conflates “the data signal” with “an internal data signal” consistent with the written description rejection of claim 1 above. That is, claim 8 recites the limitation, “at least one latch circuit suitable for latching the at least one comparison data signal as the data signal synchronized with the at least one data strobe signal.” Applicant is advised to amend claim 8 consistent with the recommendation set forth in the rejection of claim 1 above. Claim 12 is rejected because it conflates “the data signal” with “an internal data signal” consistent with the written description rejection of claim 1 above. That is, claim 12 recites the limitation, “a plurality of latch circuits suitable for latching the at least one first comparison data signal and the at least one second comparison data signal as the data signal synchronized with the at least one data strobe signal.” Applicant is advised to amend claim 12 consistent with the recommendation set forth in the rejection of claim 1 above. Claims 14 and 23 contain a defect similar to the defect identified in the written description rejection of claim 1, above. Applicant is advised to amend claims 14 and 23 similarly to the recommendation set forth in the rejection of claim 1 above. Claims 15-22 are rejected because they depend on claim 14; and therefore, contain at least the same defect(s). Claims 24-32 are rejected because they depend on claim 23; and therefore, contain at least the same defect(s). Claim 21 is rejected because it conflates “the data signal” with “an internal data signal” consistent with the written description rejection of claim 14 above. That is, claim 21 recites the limitation, “at least one latch circuit suitable for latching the at least one comparison data signal as the data signal synchronized with the data strobe signal.” Applicant is advised to amend claim 21 consistent with the recommendation set forth in the rejection of claim 14 above. Claim 27 is rejected because it conflates “the data signal” with “an internal data signal” consistent with the written description rejection of claim 23 above. That is, claim 27 recites the limitation, “a plurality of latch circuits suitable for latching the at least one first comparison data signal and the at least one second comparison data signal as the data signal synchronized with the at least one data strobe signal.” Applicant is advised to amend claim 27 consistent with the recommendation set forth in the rejection of claim 23 above. Claim 29 is rejected because it conflates “the data signal” with “an internal data signal” consistent with the written description rejection of claim 23 above. That is, claim 29 recites the limitation, “at least one latch circuit suitable for latching the at least one comparison data signal as the data signal synchronized with the at least one data strobe signal.” Applicant is advised to amend claim 29 consistent with the recommendation set forth in the rejection of claim 23 above. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Apr 03, 2024
Application Filed
Dec 01, 2025
Non-Final Rejection mailed — §112
Feb 27, 2026
Response Filed
Apr 09, 2026
Non-Final Rejection mailed — §112
Jul 07, 2026
Response Filed
Jul 31, 2026
Examiner Interview (Telephonic)
Aug 19, 2026
Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
99%
Grant Probability
99%
With Interview (+2.2%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 82 resolved cases by this examiner. Grant probability derived from career allowance rate.

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