DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US Pub. 2018/0107384).
Regarding claim 1, Fig. 7B of Shin discloses a memory device comprising:
a base semiconductor die comprising:
a first collection of circuitry [760] comprising a first physical interface (PHY) [762] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0039];
a second collection of circuitry [740] comprising a second PHY [742] arranged differently from the first PHY and electrically disconnected from the first PHY [as shows in Fig. 7B, 742 and 762 are electrically disconnected];
first contacts disposed [722] at a first side [top left] of the base semiconductor die and coupled with a first one of the first collection of circuitry [760] and the second collection of circuitry [722 couples to 740 through 720a, 750, 720b, and 724]; and
second contacts [724] disposed at a second side [bottom left] of the base semiconductor die opposite the first side, the second contacts coupled with the first one of the first collection of circuitry [724 couples to 760 through 720b, 750, 720a, and 722] and the second collection of circuitry [740]; and
one or more memory dies [within EMBEDDED UFS (universal flash storage)] coupled with the base semiconductor die through the second contacts [724].
Regarding claim 4, Fig. 7B of Shin discloses wherein the second collection of circuitry [740] further comprises logical circuitry [744 or 746] coupled with the second PHY [742] and configured to perform one or more processing in memory (PIM) operations [processing data].
Regarding claim 5, Fig. 7B of Shin discloses wherein the logical circuitry is further configured to receive signaling [RMMI] indicating that the logical circuitry is to perform the one or more PIM operations [transferring data], wherein performing the one or more PIM operations is responsive to receiving the signaling indicating that the logical circuitry is to perform the one or more PIM operations [Unipro and UTP are configured to transfer data].
Regarding claim 7, Fig. 7B of Shin discloses wherein the second collection of circuitry [740] further comprises logical circuitry [744 or 746] coupled with the second PHY and configured to: schedule a transmission of commands to the one or more memory dies; or determine an address at which data requested from the memory device is stored in the one or more memory dies [744, 746 are configured to transfer data and address to the memory device].
Regarding claim 8, Fig. 7B of Shin discloses wherein the memory device comprises a high-bandwidth memory (HBM) device [Universal Flash Storage is considered high-bandwidth memory], and the JEDEC standard comprises a JEDEC HBM standard [paragraph 0026].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 9, 11-13, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. 2018/0107384) in view of Keeth et al. (US Pub. 2020/0272564).
Regarding claims 3 and 11, Fig. 7B of Shin discloses wherein the base semiconductor die further comprises: a middle portion [724] having the second contacts; a first portion [where 760 are integrated] comprising the first collection of circuitry [760]; and a second portion [where 740 integrated] comprising the second collection of circuitry [760], wherein the first portion [760] and the second portion [740] are on opposing sides of the middle portion [760 is electrically on the other side of 724, through 720b, 750, and 720a].
Shin does not shows one or more through-silicon vias coupled with the second contacts. However, paragraph 0177 discloses a through-silicon vias connects multiple stacks of circuits together.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Shin’s memory having multiple PHY such that Shin memory device having vias to connects two circuits together according to Keeth’s teachings for the purpose increasing signal speed [paragraph 0047].
Regarding claim 9, Fig. 7B of Shin discloses a method comprising:
a first collection of circuitry [760] comprising a first physical interface (PHY) [762] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0004];
a second collection of circuitry [740] comprising a second PHY [742] arranged differently from the first PHY [762] and electrically disconnected from the first PHY [760 can be configured to be disconnected with 740 by the router 750];
coupling a first one of the first collection of circuitry [760] and the second collection of circuitry to the contacts [722]; and
coupling one or more memory dies [ROM, or memory from HOST 710] with the first one of the first collection of circuitry [760] and the second collection of circuitry through the contacts [722].
Shin discloses all claimed limitations, but does not specifically discloses a substrate comprising connective circuitry coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry. However, Fig. 2 and Fig. 3 of Keeth discloses a memory system having host 202 [Fig. 2] and memory dies [210, Fig. 2], wherein the host comprises PHY interface [312, Fig. 3], and memory dies having second and third THY [DRAM DQ PHY and DRAM CA PHY respectively]. As shows in Fig. 2, a substrate [204] comprising connective circuit [within 204] coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry [paragraphs 0043 and 0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Shin’s memory having multiple PHY such that Shin memory device lays on a substrate and the connections between host and memory dies go through the substrate according to Keeth’s teachings for the purpose of reducing chip space and increasing signal speed [paragraph 0047].
Regarding claim 12, Fig. 7B of Shin discloses wherein the second collection of circuitry further comprises logical circuitry [Unipro or UTP] coupled with the second PHY [742] and configured to perform one or more processing in memory (PIM) operations [data transferring].
Regarding claim 13, Fig. 7B of Shin discloses wherein the logical circuitry is further configured to receive signaling [RMMI] indicating that the logical circuitry is to perform the one or more PIM operations [transferring data], wherein performing the one or more PIM operations is responsive to receiving the signaling indicating that the logical circuitry is to perform the one or more PIM operations [Unipro and UTP are configured to transfer data].
Regarding claim 15, Fig. 7B of Shin discloses wherein the second collection of circuitry [740] further comprises logical circuitry [744 or 746] coupled with the second PHY and configured to: schedule a transmission of commands to the one or more memory dies; or determine an address at which data requested from the memory device is stored in the one or more memory dies [744, 746 are configured to transfer data and address to the memory device].
Regarding claim 16, Fig. 7B of Shin discloses wherein the memory device comprises a high-bandwidth memory (HBM) device [Universal Flash Storage is considered high-bandwidth memory], and the JEDEC standard comprises a JEDEC HBM standard [paragraph 0026].
Regarding claim 18, Fig. 7B of Shin discloses a semiconductor device assembly comprising:
a host device [710] comprising a processor [714] and a first collection of circuitry [720a] including a first physical interface (PHY) [720a] coupled with the processor;
a memory device comprising:
a second collection of circuitry [760] comprising a second PHY [762] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0039];
a third collection of circuitry [740] comprising a third PHY [742] arranged differently from the second PHY and electrically disconnected from the second PHY [router 750 can be configured to disconnect 760 from 740]; and
one or more memory dies [ROM or memory from HOST] coupled with a first one of the second collection [760] of circuitry and the third collection of circuitry; wherein the first PHY [720a] is disconnected from a second one [760] of the second collection of circuitry and the third collection of circuitry [720a can be disconnected from 740 by router 750].
Shin discloses all claimed limitations, but does not specifically discloses a substrate comprising connective circuitry coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry. However, Fig. 2 and Fig. 3 of Keeth discloses a memory system having host 202 [Fig. 2] and memory dies [210, Fig. 2], wherein the host comprises PHY interface [312, Fig. 3], and memory dies having second and third THY [DRAM DQ PHY and DRAM CA PHY respectively]. As shows in Fig. 2, a substrate [204] comprising connective circuit [within 204] coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry [paragraphs 0043 and 0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Shin’s memory having multiple PHY such that Shin memory device lays on a substrate and the connections between host and memory dies go through the substrate according to Keeth’s teachings for the purpose of reducing chip space and increasing signal speed [paragraph 0047].
Regarding claim 19, Fig. 7B of Shin discloses wherein the first one of the second collection of circuitry [760] and the third collection of circuitry comprises the second collection of circuitry [762].
Regarding claim 20, 7B of Shin discloses wherein the first one of the second collection of circuitry and the third collection of circuitry [740] comprises the third collection of circuitry [742].
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. 2018/0107384) in view of Keeth et al. (US Pub. 2020/0272564) and further in view of You et al. (US Pub. 2023/0044186).
Regarding claims 6 and 14, Shin in view of Keeth discloses all claimed invention, but does not specifically disclose wherein the logical circuitry comprises an artificial intelligence (AI) accelerator. However, Fig. 11 of You discloses a logical circuitry (control circuit) comprises an artificial intelligence (AI) accelerator [1820].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of You’s memory with AI accelerator to the teachings of Lin’s memory having multiple PHY such that Lin memory device having an AI accelerator according to You’s teachings for the purpose of speeding up computational tasks.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. 2018/0107384) in view of Keeth et al. (US Pub. 2020/0272564) and further in view of Ware et al. (US Pub. 2023/0185531).
Regarding claims 2 and 10, Shin in view of Keeth discloses all claimed invention, but does not specifically disclose using transistors switches to connects or disconnect first and second collection of circuits, but does not specifically discloses using fuses for the connection/disconnection. However, paragraph 0039 of Ware teaches using fuses to make connections between different circuits and blowing fuses to make the disconnection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ware’s memory using fuses for switching to the teachings of Lin’s memory having multiple PHY such that Lin memory device having fuses functions as switches according to Ware’s teachings for the purpose turning on or off a switch faster.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, the prior art does not teach or suggest either alone or in combination wherein the contacts are first contacts disposed at a first side of the semiconductor substrate, the method further comprising: disposing second contacts at a second side of the semiconductor substrate opposite the first side, the second contacts coupled with the first one of the first collection of circuitry and the second collection of circuitry; providing an additional substrate comprising third contacts at a third side, fourth contacts at the third side, and connective circuitry coupling the third contacts and the fourth contacts; providing a host device comprising a processor and fifth contacts coupled with the processor; and coupling the second contacts with the third contacts and the fifth contacts with the fourth contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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