DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 9, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite in that it fails to point out what is included or excluded by the claim language. This claim is an omnibus type claim.
Claims 1, 9, and 18 includes limitations that discloses “a first collection of circuitry comprising a first physical interface (PHY)”, “a second collection of circuitry comprising a second PHY arranged differently from the first PHY and electrically disconnected from the first PHY”. However, it also includes limitations that discloses “first contacts disposed at a first side of the base semiconductor die and coupled with a first one of the first collection of circuitry and the second collection of circuitry”. If there is contacts that couples the first PHY and the second PHY together, then the “second PHY” wont able to “electrically disconnected from the first PHY”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US Pub. 2018/0107384).
Regarding claim 1, Fig. 7B of Shin discloses a memory device comprising:
a base semiconductor die comprising:
a first collection of circuitry [760] comprising a first physical interface (PHY) [762] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0039];
a second collection of circuitry [740] comprising a second PHY [742] arranged differently from the first PHY and electrically disconnected from the first PHY [as shows in Fig. 7B, 742 and 762 are electrically disconnected];
first contacts disposed [722] at a first side [top left] of the base semiconductor die and coupled with a first one of the first collection of circuitry [760] and the second collection of circuitry [722 couples to 740 through 720a, 750, 720b, and 724]; and
second contacts [724] disposed at a second side [bottom left] of the base semiconductor die opposite the first side, the second contacts coupled with the first one of the first collection of circuitry [724 couples to 760 through 720b, 750, 720a, and 722] and the second collection of circuitry [740]; and
one or more memory dies [within EMBEDDED UFS (universal flash storage)] coupled with the base semiconductor die through the second contacts [724].
Claims 1, 4-5, 7-8 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Lin et al. (US Pub. 2022/0276939).
Regarding claim 1, Fig. 3 of Lin discloses a memory device comprising:
a base semiconductor die comprising:
a first collection of circuitry [230] comprising a first physical interface (PHY) [240, M-PHY layer] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0004];
a second collection of circuitry [within 230] comprising a second PHY [PHY adapter layer L1.5] arranged differently [PHY adapter layer L1.5 is different layer from M-PHY layer] from the first PHY and electrically disconnected from the first PHY [PHY adapter layer L1.5 functions to transfer data and control power management within the memory device 20A, M-PHY layer functions to communicate with host 10. Therefore, PHY adapter layer L1.5 is capable of electrically disconnecting from M-PHY layer];
first contacts [contacts connect to transmitter on layer 240] disposed at a first side [left] of the base semiconductor die and coupled with a first one of the first collection of circuitry [within 240] and the second collection of circuitry [within 230]; and
second contacts [contacts connect to receiver 242 or data link layer L2] disposed at a second side [right side] of the base semiconductor die opposite the first side [left], the second contacts coupled with the first one of the first collection of circuitry [within circuit 240] and the second collection of circuitry [within circuit 230]; and
one or more memory dies [29] coupled with the base semiconductor die through the second contacts [242 or data link layer L2].
Regarding claim 4, Fig. 8 of Lin discloses wherein the second collection of circuitry further comprises logical circuitry [L2] coupled with the second PHY [L1.5] and configured to perform one or more processing in memory (PIM) operations [error handling].
Regarding claim 5, Fig. 8 of Lin discloses wherein the logical circuitry [L2] is further configured to receive signaling [E1] indicating that the logical circuitry is to perform the one or more PIM operations [data error processing, paragraph 0091], wherein performing the one or more PIM operations is responsive to receiving the signaling indicating that the logical circuitry is to perform the one or more PIM operations [paragraph 0091].
Regarding claim 7, Fig. 1 and Fig. 8 of Lin discloses wherein the second collection of circuitry further comprises logical circuitry [L3 and L4 (Fig. 8) which are within controller 23 in Fig. 1] coupled with the second PHY [PHY adapter layer L1.5] and configured to: schedule a transmission of commands to the one or more memory dies [as discloses in paragraph 0039, controller 23 handle data transferring between the storage and host]; or determine an address at which data requested from the memory device is stored in the one or more memory dies [since the controller handles data transferring between the memory storage and host, it inherently determine where to store or read data base on an address].
Regarding claim 8, Fig. 1 of Lin discloses wherein the memory device comprises a high-bandwidth memory (HBM) device [29], and the JEDEC standard comprises a JEDEC HBM standard [paragraph 0004].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 9, 11-13, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Pub. 2022/0276939) in view of Keeth et al. (US Pub. 2020/0272564).
Regarding claims 3 and 11, Fig. 3 of Lin discloses wherein the base semiconductor die further comprises: a middle portion [L2] having the second contacts; a first portion comprising the first collection of circuitry [bottom layer of L2]; and a second portion [top of L2] comprising the second collection of circuitry, wherein the first portion and the second portion are on opposing sides of the middle portion.
Lin does not shows one or more through-silicon vias coupled with the second contacts. However, paragraph 0177 discloses a through-silicon vias connects multiple stacks of circuits together.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Lin’s memory having multiple PHY such that Lin memory device having vias to connects two circuits together according to Keeth’s teachings for the purpose increasing signal speed [paragraph 0047].
Regarding claim 9, Fig. 3 of Lin discloses a method comprising:
a first collection of circuitry [within 240] comprising a first physical interface (PHY) [M-PHY layer] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0004];
a second collection of circuitry [within 230] comprising a second PHY [PHY adapter layer L1.5] arranged differently from the first PHY [M-PHY layer] and electrically disconnected from the first PHY [PHY adapter layer L1.5 functions to transfer data and control power management within the memory device 20A, M-PHY layer functions to communicate with host 10. Therefore, PHY adapter layer L1.5 is capable of electrically disconnecting from M-PHY layer];
coupling a first one of the first collection of circuitry and the second collection of circuitry to the contacts [circuit within 240 and 230 are coupled together to transfer data between host 10 and memory device 29]; and
coupling one or more memory dies [29] with the first one of the first collection of circuitry [240] and the second collection of circuitry [within 230] through the contacts [data link layer L2].
Lin discloses all claimed limitations, but does not specifically discloses a substrate comprising connective circuitry coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry. However, Fig. 2 and Fig. 3 of Keeth discloses a memory system having host 202 [Fig. 2] and memory dies [210, Fig. 2], wherein the host comprises PHY interface [312, Fig. 3], and memory dies having second and third THY [DRAM DQ PHY and DRAM CA PHY respectively]. As shows in Fig. 2, a substrate [204] comprising connective circuit [within 204] coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry [paragraphs 0043 and 0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Lin’s memory having multiple PHY such that Lin memory device lays on a substrate and the connections between host and memory dies go through the substrate according to Keeth’s teachings for the purpose of reducing chip space and increasing signal speed [paragraph 0047].
Regarding claim 12, Fig. 8 of Lin discloses wherein the second collection of circuitry further comprises logical circuitry [L2] coupled with the second PHY [L1.5] and configured to perform one or more processing in memory (PIM) operations [error handling].
Regarding claim 13, Fig. 8 of Lin discloses wherein the logical circuitry [L2] is further configured to receive signaling [E1] indicating that the logical circuitry is to perform the one or more PIM operations [data error processing, paragraph 0091], wherein performing the one or more PIM operations is responsive to receiving the signaling indicating that the logical circuitry is to perform the one or more PIM operations [paragraph 0091].
Regarding claim 15, Fig. 1 and Fig. 8 of Lin discloses wherein the second collection of circuitry further comprises logical circuitry [L3 and L4 (Fig. 8) which are within controller 23 in Fig. 1] coupled with the second PHY [PHY adapter layer L1.5] and configured to: schedule a transmission of commands to the one or more memory dies [as discloses in paragraph 0039, controller 23 handle data transferring between the storage and host]; or determine an address at which data requested from the memory device is stored in the one or more memory dies [since the controller handles data transferring between the memory storage and host, it inherently determine where to store or read data base on an address].
Regarding claim 16, Fig. 1 of Lin discloses wherein the memory device comprises a high-bandwidth memory (HBM) device [29], and the JEDEC standard comprises a JEDEC HBM standard [paragraph 0004].
Regarding claim 18, Fig. 3 of Lin discloses a semiconductor device assembly comprising:
a host device [10] comprising a processor [13, Fig. 1] and a first collection of circuitry [host interface 15, Fig. 1] including a first physical interface (PHY) [M-PHY layer, 140] coupled with the processor;
a memory device comprising:
a second collection of circuitry [within 240] comprising a second PHY [M-PHY layer] arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard [paragraph 0004];
a third collection of circuitry [within 230] comprising a third PHY [PHY adapter layer L1.5] arranged differently from the second PHY and electrically disconnected from the second PHY [PHY adapter layer L1.5 functions to transfer data and control power management within the memory device 20A, M-PHY layer functions to communicate with host 10. Therefore, PHY adapter layer L1.5 is capable of electrically disconnecting from M-PHY layer]; and
one or more memory dies [29] coupled with a first one of the second collection of circuitry and the third collection of circuitry; wherein the first PHY [M-PHY layer 140] is disconnected from a second one [M-PHY layer 240] of the second collection of circuitry and the third collection of circuitry [there are switches that controls connection between host 10 and memory die 20A, the connection can be controlled to be on or off].
Lin discloses all claimed limitations, but does not specifically discloses a substrate comprising connective circuitry coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry. However, Fig. 2 and Fig. 3 of Keeth discloses a memory system having host 202 [Fig. 2] and memory dies [210, Fig. 2], wherein the host comprises PHY interface [312, Fig. 3], and memory dies having second and third THY [DRAM DQ PHY and DRAM CA PHY respectively]. As shows in Fig. 2, a substrate [204] comprising connective circuit [within 204] coupling the first collection of circuitry to the first one of the second collection of circuitry and the third collection of circuitry [paragraphs 0043 and 0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Keeth’s memory with PHY to the teachings of Lin’s memory having multiple PHY such that Lin memory device lays on a substrate and the connections between host and memory dies go through the substrate according to Keeth’s teachings for the purpose of reducing chip space and increasing signal speed [paragraph 0047].
Regarding claim 19, Fig. 3 of Lin discloses wherein the first one of the second collection of circuitry [within 130] and the third collection [within 230] of circuitry comprises the second collection of circuitry [PHY adapter layer L1.5].
Regarding claim 20, Fig. 3 of Lin discloses wherein the first one of the second collection of circuitry [within 240] and the third collection of circuitry [within 230] comprises the third collection of circuitry [PHY adapter layer L1.5, within 230].
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Pub. 2022/0276939) in view of Keeth et al. (US Pub. 2020/0272564) and further in view of You et al. (US Pub. 2023/0044186).
Regarding claims 6 and 14, Lin in view of Keeth discloses all claimed invention, but does not specifically disclose wherein the logical circuitry comprises an artificial intelligence (AI) accelerator. However, Fig. 11 of You discloses a logical circuitry (control circuit) comprises an artificial intelligence (AI) accelerator [1820].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of You’s memory with AI accelerator to the teachings of Lin’s memory having multiple PHY such that Lin memory device having an AI accelerator according to You’s teachings for the purpose of speeding up computational tasks.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Pub. 2022/0276939) in view of Keeth et al. (US Pub. 2020/0272564) and further in view of Ware et al. (US Pub. 2023/0185531).
Regarding claims 2 and 10, Lin in view of Keeth discloses all claimed invention, but does not specifically disclose using transistors switches to connects or disconnect first and second collection of circuits, but does not specifically discloses using fuses for the connection/disconnection. However, paragraph 0039 of Ware teaches using fuses to make connections between different circuits and blowing fuses to make the disconnection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ware’s memory using fuses for switching to the teachings of Lin’s memory having multiple PHY such that Lin memory device having fuses functions as switches according to Ware’s teachings for the purpose turning on or off a switch faster.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, the prior art does not teach or suggest either alone or in combination wherein the contacts are first contacts disposed at a first side of the semiconductor substrate, the method further comprising: disposing second contacts at a second side of the semiconductor substrate opposite the first side, the second contacts coupled with the first one of the first collection of circuitry and the second collection of circuitry; providing an additional substrate comprising third contacts at a third side, fourth contacts at the third side, and connective circuitry coupling the third contacts and the fourth contacts; providing a host device comprising a processor and fifth contacts coupled with the processor; and coupling the second contacts with the third contacts and the fifth contacts with the fourth contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825