DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claims 3, 7, 8, 11, 14, 16, 18, and 19 are withdrawn.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to KR10-2023-0139876 for 10/18/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant's election with traverse of Species II, Subspecies I, including claims 1, 2, 5, 6, 10, 12, 13, 15, 17, and 20 in the reply filed on 06/18/2026 is acknowledged. The traversal is on the grounds that overlapping common elements would naturally be found during search. This is not found persuasive because overlapping common elements to the species do not negate mutually exclusive limitations to the claims, nor burden in searching the mutually exclusive limitations, such as at least layer orientation of the dielectric film in reference to electrodes and contact plugs.
The requirement is still deemed proper and is therefore made FINAL.
Claims 3, 7, 8, 11, 14, 16, 18, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species and subspecies, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 06/18/2026.
Claims 4 and 9, not elected, but not corresponding to an individual species or subspecies, will be examined.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/03/2024 and 05/13/2026 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
VERTICAL MEMORY DEVICE INCLUDING VERTICAL WORD LINES SURROUNDING CHANNEL LINES AND BACK GATE ELECTRODES
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda et al. (US PGPub 2020/0111916; herein known as Karda).
Regarding claim 1, Karda teaches (annotated Fig. 1A below) a semiconductor memory device comprising:
a conductive line (104, [0067]) extending lengthwise in a first horizontal direction (x-direction);
first (118, [0086]) and second (118, [0086]) channel regions over the conductive line and apart from each other in the first horizontal direction, each of the first and second channel regions configured to be connected to the conductive line (through 105, [0027]);
a plurality of contact plugs (126, [0037]) apart from the conductive line in a vertical direction (z-direction) with the first and second channel regions therebetween, the plurality of contact plugs aligned in the first horizontal direction (x-direction);
a back gate electrode (108, [0036]) extending lengthwise in a second horizontal direction (y-direction) between the first and second channel regions, the back gate electrode being apart from the conductive line and each of the plurality of contact plugs in the vertical direction (z-direction), the second horizontal direction being perpendicular to the first horizontal direction;
and a back gate dielectric film (112, [0036]) covering surfaces of the back gate electrode, wherein the back gate dielectric film comprises a vertical extension portion (VP) and a horizontal extension portion (HP), the vertical extension portion being between the back gate electrode and the first channel region and between the back gate electrode and the second channel region and covering sidewalls of the back gate electrode, the horizontal extension portion integrally connected to the vertical extension portion and covering an end surface of the back gate electrode at a position facing the plurality of contact plugs.
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Regarding claim 2, Karda teaches (annotated Fig. 1A below) the semiconductor memory device of claim 1, wherein the back gate electrode (108, [0036]) has a first end surface (ES1) facing the conductive line (104, [0067]) and a second end surface (ES2) facing the plurality of contact plugs (126, [0037]), and the horizontal extension portion (HP) of the back gate dielectric film (112, [0036]) is apart from the plurality of contact plugs in the vertical direction and is in contact with the second end surface of the back gate electrode (see figure below).
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Regarding claim 4, Karda teaches (Fig. 1A) the semiconductor memory device of claim 1, further comprising: a first capping insulating pattern (216, []) being between the first channel region and the second channel region (between the first and second channel region in the horizontal direction), overlapping the back gate electrode (208, []) in the vertical direction, and located between the back gate electrode and the plurality of contact plugs (126, []); and a second capping insulating pattern (206, []) being between the first channel region and the second channel region, overlapping the back gate electrode in the vertical direction, and located between the back gate electrode and the conductive line (102, []), wherein the horizontal extension portion of the back gate dielectric film is between the back gate electrode and the first capping insulating pattern (see figure).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Karda as applied to claim 1 above, and further in view of Juengling et al. (US PGPub 2021/0134815; herein known as Juengling).
Regarding claim 5, Karda teaches (Fig. 2J, a simplified equivalent embodiment to Fig. 1A) the semiconductor memory device of claim 1, further comprising: a first capping insulating pattern (216, [0080]) being between the first channel region and the second channel region (between the first and second channel region in the horizontal direction), overlapping the back gate electrode (208, [0082]) in the vertical direction, and located between the back gate electrode (208) and the plurality of contact plugs (126, [0037]), and the horizontal extension portion (HP) of the back gate dielectric film is between the first capping insulating pattern (216) and the back gate electrode (208) and is apart from the first and second contact plugs in the vertical direction (see figure below), but does not explicitly teach wherein the plurality of contact plugs comprise a first contact plug connected to the first channel region and a second contact plug connected to the second channel region.
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Juengling teaches (Fig. 35) the plurality of contact plugs (68, [0057]) comprise a first contact plug (68 of 54e) connected to the first channel region (58 of 54e) and a second contact plug (68 of 54f) connected to the second channel region (58 of 54f).
Because Karda and Juengling are both directed toward vertical transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Karda and of Juengling to include wherein the plurality of contact plugs comprise a first contact plug connected to the first channel region and a second contact plug connected to the second channel region in order to individually couple capacitors to respective transistors in order to form individual memory cells (Juengling, [0059]).
Regarding claim 6, Karda in view of Juengling teaches (Karda, Fig. 1A) the semiconductor memory device of claim 5, wherein the vertical extension portion of the back gate dielectric film is in contact with the conductive line (lower conductive contact 105 is optional, and back gate dielectric film 112 would thus be in physical contact with conductive line 104 in its absence, see Fig. 2F, [0076]).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the semiconductor memory device of claim 1, further comprising: a pair of word lines each being between the second channel region and the third channel region and apart from each other in the first horizontal direction, the pair of word lines including a first word line relatively closer to the second channel region and a second word line relatively closer to the third channel region.
Karda teaches wherein the central electrode 108 functions as a word line and further teaches a conductive shielding layer 120 disposed between the second and third channel region and apart from each other in the first horizontal direction. However, Karda does not teach nor suggest a motivation to modify the shielding layer to instead function as a word line, teaching wherein the shielding layer is used to prevent word line capacitance between adjacent word lines. Juengling teaches adjacent word lines (Fig. 35, 56) but teaches where these are directly adjacent to a central channel region, with no electrode present. Additionally, modification of Karda in view of Juengling to include the word lines of Juengling would functionally change the device of Karda, and absent a direct teaching of the use of the shielding layers of Karda as word lines, one of ordinary skill in the art would not be motivated to combine the teachings of Karda and Juengling to include a pair of word lines each being between the second channel region and the third channel region and apart from each other in the first horizontal direction, the pair of word lines including a first word line relatively closer to the second channel region and a second word line relatively closer to the third channel region.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claim 10 is allowable as dependent on claim 9, pending the objection to claim 9 as being dependent on a rejected base claim.
Claims 12, 13, 15, 17, and 20 are allowed.
Regarding claim 12, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor memory device comprising a first word line apart from the back gate electrode in the first horizontal direction with the first channel region therebetween; a second word line apart from the back gate electrode in the first horizontal direction with the second channel region therebetween.
Karda teaches wherein the central electrode 108 functions as a word line and further teaches a conductive shielding layer 120 disposed between the second and third channel region and apart from each other in the first horizontal direction. However, Karda does not teach nor suggest a motivation to modify the shielding layer to instead function as a word line, teaching wherein the shielding layer is used to prevent word line capacitance between adjacent word lines. Juengling teaches adjacent word lines (Fig. 35, 56) but teaches where these are directly adjacent to a central channel region, with no electrode present. Additionally, modification of Karda in view of Juengling to include the word lines of Juengling would functionally change the device of Karda, and absent a direct teaching of the use of the shielding layers of Karda as word lines, one of ordinary skill in the art would not be motivated to combine the teachings of Karda and Juengling to include a pair of word lines each being between the second channel region and the third channel region.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claims 13, 15, and 17 are allowed as dependent on claim 12.
Regarding claim 20, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor memory device comprising: a plurality of word lines extending lengthwise in the second horizontal direction and between the plurality of conductive lines and the plurality of contact plugs, wherein the plurality of word lines are arranged such that each pair of adjacent word lines selected from the plurality of word lines are between a pair of back gate electrodes selected from among the plurality of back gate electrodes.
Karda teaches wherein the central electrode 108 functions as a word line and further teaches a conductive shielding layer 120 disposed between the second and third channel region and apart from each other in the first horizontal direction. However, Karda does not teach nor suggest a motivation to modify the shielding layer to instead function as a word line, teaching wherein the shielding layer is used to prevent word line capacitance between adjacent word lines. Juengling teaches adjacent word lines (Fig. 35, 56) but teaches where these are directly adjacent to a central channel region, with no electrode present. Additionally, modification of Karda in view of Juengling to include the word lines of Juengling would functionally change the device of Karda, and absent a direct teaching of the use of the shielding layers of Karda as word lines, one of ordinary skill in the art would not be motivated to combine the teachings of Karda and Juengling to include a pair of word lines each being between the second channel region and the third channel region.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/EMILY FARMER/Examiner, Art Unit 2812
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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