Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Specifically, the term “primarily composed of” renders the metes and bounds of the claim unclear as it is a term of degree. A high Al content is assumed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20220052166 to Yeh et al. (Yeh).
Regarding Claim 1, Yeh teaches a semiconductor device, comprising:
a depletion mode [0022] gallium nitride field effect transistor 100 (GaN FET), including:
a channel layer 22 of III-N semiconductor material, the channel layer including gallium and nitrogen [0024];
a barrier layer 24 of III-N semiconductor material over the channel layer, the barrier layer including aluminum and nitrogen [0025];
a gate 26 of III-N semiconductor material over the barrier layer, the gate being p-type, the gate including gallium and nitrogen [0028];
a source 40A contacting the channel layer; and
a drain 40B contacting the channel layer; wherein:
a bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, the top surface being located opposite from the channel layer (see Fig. 1);
the GaN FET is free of a dielectric layer between the gate and the barrier layer; but does not explicitly teach that the GaN FET has a gate-source threshold potential of -10 volts to -0.5 volts.
However, Yeh teaches that the electrical parameters including threshold voltage may be optimized by adjusting the ratio of the distance S1 and the distance S2, the stress and/or the electric field of the contact structure 40A and the contact structure 40B applied to the high electron mobility transistor 100 may be adjusted, thereby optimizing the electrical parameters of the high electron mobility transistor 100 [0030], see MPEP 2144.05(II)(B).
Regarding Claim 2, Yeh teaches the semiconductor device of claim 1, but does not explicitly teach that the barrier layer has a thickness of 1 nanometer to 60 nanometers. However, Yeh teaches that the electrical parameters including threshold voltage may be optimized by selecting the materials and adjusting the thickness of each of the semiconductor thin layers, the band structure, the strength of the polarization field and/or the carrier distribution near the junction 25 may be adjusted, thereby adjusting the carrier distribution and carrier mobility of the two-dimensional electron gas layer 2DEG for product requirements [0026], see MPEP 2144.05(II)(B).
Regarding Claims 3 and 4, Yeh teaches the semiconductor device of claim 1, wherein the barrier layer includes gallium or indium [0025].
Regarding Claim 5, Yeh teaches the semiconductor device of claim 1, wherein the channel layer has a two-dimensional electron gas (2DEG) with a free charge carrier density of 3 × 1012 cm-2 to 2 × 1013 cm-2 (see above regarding optimization of parameters).
Regarding Claim 6, Yeh teaches the semiconductor device of claim 1, wherein the gate is 5 nanometers to 500 nanometers thick (see above regarding optimization of parameters).
Regarding Claim 10, Yeh teaches the semiconductor device of claim 1, wherein the GaN FET further includes a dielectric layer 52 over the barrier layer between the gate and the source, and between the gate and the drain.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20100258841 to Lidow et al. (Lidow).
Regarding Claim 7, Yeh teaches the semiconductor device of claim 1, but does not explicitly teach that the gate has a magnesium concentration of 1 × 1017 cm-3 to 1 × 1020 cm-3.
However, in analogous art, Lidow teaches a Mg concentration in p-type gate layer 57 of 1E16 to 5E19. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Lidow since Yeh is silent regarding Mg concentration, motivating those of ordinary skill to seek out such teachings. See also MPEP 2144.05(I).
Regarding Claim 8, Yeh and Lidow teach the semiconductor device of claim 1, wherein the GaN FET further includes a high bandgap sublayer 28 between the channel layer and the barrier layer, the high bandgap sublayer including primarily aluminum and nitrogen, the high bandgap sublayer being 0.5 nanometers to 3 nanometers thick [0028].
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20210376136 to Akutsu et al. (Akutsu).
Regarding Claim 7, Yeh teaches the semiconductor device of claim 1, but does not explicitly teach that the GaN FET further includes an etch stop layer between the barrier layer and the gate, the etch stop layer having a higher aluminum content than the barrier layer, the etch stop layer being 0.5 nanometers to 3 nanometers thick.
However, Akutsu teaches an etch stop layer 6 having a higher aluminum content than a barrier layer 5 between .5 and 2 nm [0062-0063]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Akutsu to protect the barrier layer during etching processes.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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