Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, Figs. 8A-10, in the reply filed on July 2, 2026, is acknowledged.
Claims 5-6, 10-11, and 15-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 2, 2026.
Claim Objections
Claim 2 is objected to because of the following informalities: the limitation, “wherein the conductive pattern includes a conductive material”, seems redundant, as the choice of the term, “conductive pattern”, would appear to necessarily imply that it is made of a conductive material. Appropriate correction is required.
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Fig. 1 of Roh, reproduced with annotation added by the examiner.
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Fig. 2A of Roh, reproduced with annotations added by the examiner.
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Fig. 3 of Roh, reproduced with annotations added by the examiner.
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Fig. 6 of Roh, reproduced with annotations and lines showing the division of each of the power pad and the second insulating layer into two parts added by the examiner.
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Figs. 7 and 8 of Roh, reproduced with annotations and lines showing part of the lower conductive layer and the protrusions in the power pad added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Roh et. al., Pub. No. US 2020/0271979, hereafter referred to as Roh.
Regarding claim 17, Roh teaches all of the limitations of the claim in Figs. 1, 2A, and 6-8, reproduced above with annotations added by the examiner: “A display device” (Roh [0063]; Fig. 1, display device 1), “comprising: a display module” (Roh [0066]; Fig. 1, display panel 100) “including: a pixel” (Roh [0062]; Fig. 2A); “a signal line electrically connected to the pixel” (Roh [0078]; Figs. 2A and 3, gate signal line GSL); “and a signal pad electrically connected to the signal line” (Roh [0106]; Fig. 3, note that the wire pads PAD are connected to the gate signal lines GSL), “wherein the signal pad includes: an insulating pattern disposed on the signal line” (Roh [0079] and [0122]; Fig. 7, note that the second insulating layer 112b is in contact with the gate signal line GSL); “and a conductive pattern electrically connected to the signal line” (Roh [0082]; Fig. 7, power pad PW_PAD1; note that the power pad PW_PAD1 is in contact with the gate signal line GSL; also see Fig. 3, noting that the power pad PW_PAD1 is included among the plurality of pads PAD), “and at least a portion of the conductive pattern has a form of a plurality of protrusions protruding from the insulating pattern, when viewed in a cross-sectional view” (Roh [0082]; Figs. 7 and 8, note that the power pad PW_PAD1 has bumps over the second insulating layer 112b).
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Fig. 6 of Oh, reproduced with annotations added by the examiner.
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Alternate reproduction of Fig. 6 of Oh, showing a mockup prepared by the examiner of the lower portion of the mesh in the combined device of Roh and Oh described in the discussions of claims 1 and 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 7, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Roh et. al., Pub. No. US 2020/0271979, hereafter referred to as Roh, in view of Oh et. al., Pub. No. US 2015/0248186, hereafter referred to as Oh.
Regarding claim 1, Roh teaches “A display device” (Roh [0063]; Fig. 1, display device 1), “comprising: a display module” (Roh [0066]; Fig. 1, display panel 100) “including: a pixel” (Roh [0062]: “Specifically, FIG. 2A is a cross-sectional view illustrating a pixel area and a panel pad area P_PA of FIG. 1.”; Fig. 2A); “a signal line electrically connected to the pixel” (Roh [0078]; Figs. 2A and 3, gate signal line GSL); “and a signal pad electrically connected to the signal line” (Roh [0106]; Fig. 3, note that the wire pads PAD are connected to the gate signal lines GSL), “wherein the signal pad includes: an insulating pattern disposed on the signal line” (Roh [0079] and [0122]; Fig. 7, note that the second insulating layer 112b is in contact with the gate signal line GSL); “and a conductive pattern electrically connected to the signal line” (Roh [0122]; Fig. 7, power pad PW_PAD1; note that the power pad PW_PAD1 is in contact with the gate signal line GSL; also see Fig. 3, noting that the power pad PW_PAD1 is included among the plurality of pads PAD), but does not teach “the conductive pattern includes: a first part including a mesh pattern; and a second part surrounding the first part; and at least a portion of the first part is disposed on the insulating pattern”. Roh, however, does teach that the signal pad has portions disposed on the top of the second insulating layer (Roh [0079] and [0122] Figs. 7 and 8; note that portions of the power pad PW_PAD1 are disposed on top of the second insulating layer 112b) and portions disposed on the gate signal line (Roh [0079] and [0122]; Figs. 7 and 8, note that portions of the power pad PW_PAD1 are disposed on top of the gate signal line GSL).
Oh, on the other hand, teaches a pad (Oh [0056]; Fig. 6, pad part 230) composed of a mesh (Oh [0056]; Fig. 6, pad 233) with a border (Oh [0056]; outline 236). In addition, Oh teaches that forming the pad as a mesh would help to alleviate the possibility of a metal pad being disconnected from a fine connecting wire during an etching process (Oh [0006]: “However, since fine line widths, such as those of the conductive lines, require an etching rate different from that used in the formation of a pad formed of a metal, the conductive lines of electrodes disposed on the periphery of the pads may be disconnected.”).
The pads with mesh patterns of Oh can be incorporated into the device of Roh by replacing the power pad of Roh with a mesh with an outline, disposed on the second insulating layer, and with a lower portion connecting the mesh to the gate signal line (see above mockup based on Oh Fig. 6 prepared by the examiner). The combined device teaches “the conductive pattern includes: a first part including a mesh pattern” (Oh [0056]; Fig. 6, pad 233); “and a second part surrounding the first part” (Oh [0056]; outline 236); “and at least a portion of the first part is disposed on the insulating pattern” (Roh [0079] and [0122]; Figs. 7 and 8; power pad PW_PAD1 and second insulating layer 112b; Oh [0056]; Fig. 6, pad 233; note that the upper mesh would contact the second insulating layer 112b in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use pads consisting of a mesh with a border as taught by Oh in the device of Roh because doing so would alleviate the possibility of the pad being disconnected from the connecting wire during an etching process (Oh [0006]) and it would be a simple substitution of one element for another.
Regarding claim 3, the combination of Roh and Oh described in the discussion of claim 1 further teaches “The display device of claim 1, wherein the mesh pattern includes: first mesh lines extending in a first direction, and disposed in a second direction intersecting the first direction” (Oh Fig. 6; note that some of the mesh lines in pad 233 extend in the first direction and are disposed in the second direction); “and second mesh lines extending in the second direction and disposed in the first direction while intersecting the first mesh lines” (Oh Fig. 6; note that some of the mesh lines in pad 233 extend in the second direction, are disposed in the first direction, and intersect the first set of mesh lines).
Regarding claim 4, the combination of Roh and Oh as applied to claim 1 above further teaches “The display device of claim 3, wherein the insulating pattern includes a plurality of insulating patterns” (Roh Fig. 6; portions of the second insulating layer 112b), “the first part includes a plurality of first parts” (Roh Fig. 6; note that there are multiple power pads PW_PAD1), “and each of the plurality of first parts is disposed on a relevant insulating pattern among the plurality of insulating patterns” (Roh Fig. 6; note that each power pad PW_PAD1 is disposed within a portion of the second insulating layer 112b).
Regarding claim 7, the combination of Roh and Oh as applied to claim 1 above teaches “The display device of claim 3, wherein the insulating pattern includes a plurality of insulating patterns” (Roh Fig. 6; portions of the second insulating layer 112b) but does not explicitly teach “and the plurality of insulating patterns are disposed in at least one of the first direction and the second direction”. Instead, the first and second directions recited in claim 3 are diagonal with respect to the border around the mesh (Oh Fig. 6; note that the mesh lines in the pad 233 are diagonal with respect to the outline 236).
Oh, on the other hand, does not teach that the specific orientation of the mesh lines is important.
The mesh lines of Oh may be rotated 45 degrees so that they are parallel to the outline. The combined device teaches “and the plurality of insulating patterns are disposed in at least one of the first direction and the second direction” (Roh Fig. 6; note that the second insulating layers 112b are now disposed along one of the first or second direction in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have rotated the mesh lines by 45 degrees in the combined device of Roh and Oh as applied to claim 1 above because the pad would still function just as well with the different orientation of the mesh lines and it would be a simple substitution of one element for another.
Regarding claim 18, Roh teaches “The display device of claim 17” but does not teach “wherein the at least a portion of the conductive pattern includes: first mesh lines extending in a first direction, and disposed in a second direction intersecting the first direction; and second mesh lines extending in the second direction and disposed in the first direction while intersecting the first mesh lines, the first mesh lines provide the form of the plurality of protrusions, when viewed in a cross-sectional view in the first direction, and the second mesh lines provide the form of the plurality of protrusions, when viewed in a cross-sectional view in the second direction.”
Oh, on the other hand, teaches a pad (Oh [0056]; Fig. 6, pad part 230) composed of a mesh (Oh [0056]; Fig. 6, pad 233) with a border (Oh [0056]; outline 236). In addition, Oh teaches that forming the pad as a mesh would help to alleviate the possibility of a metal pad being disconnected from a fine connecting wire during an etching process (Oh [0006]: “However, since fine line widths, such as those of the conductive lines, require an etching rate different from that used in the formation of a pad formed of a metal, the conductive lines of electrodes disposed on the periphery of the pads may be disconnected.”). Furthermore, Oh does not teach that the specific orientation of the mesh lines is important.
The pads with mesh patterns of Oh can be incorporated into the device of Roh by replacing the power pad of Roh with a mesh with an outline, disposed on the second insulating layer such that the mesh lines run along the second insulating layer where the bumps in the pad of Roh are located, and with a lower portion connecting the mesh to the gate signal line (see above mockup based on Oh Fig. 6 prepared by the examiner). The combined device teaches “wherein the at least a portion of the conductive pattern includes: first mesh lines extending in a first direction, and disposed in a second direction intersecting the first direction” (Roh Figs. 6 and 7; Oh [0056]; Fig. 6, pad 233 and outline 236; note that the first mesh lines would extend into the page and run parallel to the second insulating layer 112b in the combined device from the perspective of Fig. 7, i.e., the direction into and out of the page from the perspective of Fig. 7 is the first direction); “and second mesh lines extending in the second direction and disposed in the first direction while intersecting the first mesh lines” (Roh Figs. 6 and 8; Oh [0056]; Fig. 6, pad 233 and outline 236; note that the second mesh lines would extend into the page and run parallel to the second insulating layer 112b in the combined device from the perspective in Fig. 8, i.e., the direction into and out of the page from the perspective of Fig. 8 is the second direction), “the first mesh lines provide the form of the plurality of protrusions, when viewed in a cross-sectional view in the first direction” (Roh Figs. 6 and 7; Oh [0056]; Fig. 6, pad 233 and outline 236; note that the first mesh lines would run parallel to the second insulating layer 112b in the combined device from the perspective of Fig. 7), “and the second mesh lines provide the form of the plurality of protrusions, when viewed in a cross-sectional view in the second direction” (Roh Figs. 6 and 8; Oh [0056]; Fig. 6, pad 233 and outline 236; note that the second mesh lines would run parallel to the second insulating layer 112b in the combined device from the perspective in Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use pads consisting of a mesh with a border as taught by Oh in the device of Roh because doing so would alleviate the possibility of the pad being disconnected from the connecting wire during an etching process (Oh [0006]) and it would be a simple substitution of one element for another.
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Fig. 9 of Eom, reproduced with annotations added by the examiner.
Claims 2, 9, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Roh and Oh in further view of Eom et. al., Pub. No. US 2021/0337673, hereafter referred to as Eom.
Regarding claim 2, the combination of Roh and Oh described in the description of claim 1 teaches “The display device of claim 1, wherein the conductive pattern includes a conductive material” (Roh [0082]; Figs. 3 and 6, note that the pad PW_PAD1 is part of the third conductive layer 140), but does not teach “and the insulating pattern includes a polymer.”
Eom, on the other hand, teaches a similar device (Eom [0076]; Fig. 9, display device 1) with a pad (Eom [0138]; Fig. 9, film attachment pad PAD2) disposed over several insulating layers (Eom [0118] and [0130]; Fig. 9, via layer 114 and first and second touch insulating layers 131 and 132). Furthermore, Eom teaches that the via layer 114 may be made from polyimide, which is a polymer (Eom [0118]: “The via layer 114 may include acrylate or polyimide.”).
The teaching that the via layer of Eom may be made of polyimide can be incorporated into the combined device of Roh and Oh described in the description of claim 1 by making the second insulating layer out of polyimide. The combined device teaches “and the insulating pattern includes a polymer” (Roh [0079]; Fig. 2A, second insulating layer 112b; Eom [0118]; note that the second insulating layer 112b of Roh is made of polyimide in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the second insulating layer of the combined device of Roh and Oh described in the description of claim 1 out of polyimide as suggested by Eom because polyimide can serve the purpose of forming an insulating layer and it would be a simple substitution of one material for another.
Regarding claim 9, the combination of Roh and Oh described in the discussion of claim 1 teaches “The display device of claim 1”, but does not teach “wherein the display module further includes a pad insulating layer between the signal line and the conductive pattern, and the pad insulating layer has a contact hole defined in the pad insulating layer, spaced apart from the insulating pattern, and overlapping a portion of the signal line.”
Eom, on the other hand, teaches two insulating layers (Eom [0130]; Fig. 9, first and second touch insulating layers 131 and 132) interposed between a contact pad (Eom [0138]; Fig. 9, film attachment pad PAD2) and another insulating layer (Eom [0118]; Fig. 9, via layer 114) and which have vias (Eom [0161]; Fig. 9, second contact hole CNT2). In addition, the vias overlap a portion of a gate connection electrode (Eom [0111]; Fig. 9, note that the second contact holes CNT2 overlap the gate connection electrode GCE). Furthermore, Eom teaches that the purpose of the additional insulating layers is to help prevent driving failures due to shorts between pads (Eom [0004]).
The additional insulating layers of Eom can be incorporated into the combined device of Roh and Oh described in the discussion of claim 1 by adding additional insulating layers between the pad and the second insulating layer. The combined device teaches “wherein the display module further includes a pad insulating layer between the signal line and the conductive pattern” (Eom [0130]; Fig. 9, first and second touch insulating layers 131 and 132), “and the pad insulating layer has a contact hole defined in the pad insulating layer, spaced apart from the insulating pattern” (Eom [0130]; Fig. 9, note that the first and second touch insulating layers 131 and 132 have contact holes CNT2), “and overlapping a portion of the signal line” (Roh [0079] and [0122]; Fig. 7, power pad PW_PAD1 and second insulating layer 112b; Oh [0056]; Fig. 6, pad 233 and outline 236; Eom [0130]; Fig. 9, note that the first and second touch insulating layers 131 and 132 have contact holes CNT2; also note that the lower portion of the mesh contacts the gate signal line GSL through the contact holes in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to add additional insulating layers between the pad and the second insulating layer of the combined device of Roh and Oh described in the discussion of claim 1 as taught by Eom because the additional layers would provide greater protection against electrical shorts between the power pad and the gate signal line and it would be a simple combination of elements of the two disclosures.
Regarding claim 12, the combination of Roh, Oh, and Eom described in the discussion of claim 9 teaches “The display device of claim 9, wherein the signal pad further includes a lower conductive pattern disposed under the conductive pattern” (Roh [0122]; Fig. 7, power pad PW_PAD1 and gate signal wire GSL; Oh Fig. 6, mesh 233 and outline 236; note that there is a lower portion of the mesh connecting the upper portion of the mesh to the gate signal wire GSL in the combined device) “and contacting the signal line through the contact hole” (Roh [0122]; Fig. 7, power pad PW_PAD1 and gate signal wire GSL; Oh Fig. 6, mesh 233 and outline 236; note that the lower portion of the mesh is connected to the gate signal wire GSL in the combined device), but does not teach “and the insulating pattern is between the lower conductive pattern and the conductive pattern”. Roh, however, does teach an insulating via layer disposed over the power pad (Roh [0083]: “The third conductive layer 140 may include… a wire pad PAD.” and [0084]: “The first via layer VIA1 may be disposed on the third conductive layer 140. The first via layer VIA1 may include an organic insulating material.”), but it is made of a different material than the second insulating layer 112b (Roh [0077]: “The first insulating layer 111 may be a gate insulating film having a gate insulation function. In an exemplary embodiment, the first insulating layer 111 may include a silicon compound, a metal oxide, or the like. In an exemplary embodiment, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, and these materials may be used alone or in combination with one another, for example.” and [0079]: “The second insulating layer (112a and 112b) may include at least one of the aforementioned exemplary materials of the first insulating layer 111.”).
The materials disclosed by Roh for the first and second insulating layers can be incorporated into the combined device of Roh, Oh, and Eom by making the via layer out of the same material. The combined device teaches “and the insulating pattern is between the lower conductive pattern and the conductive pattern” (Roh [0084] and [0122]; Fig. 2A, via layer VIA1, and Fig. 7, power pad PW_PAD1 and gate signal wire GSL; Oh Fig. 6, mesh 233 and outline 236; note that the second insulating layer 112b and the via layer VIA1 are made of the same material in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the via layer of the combined device of Roh, Oh, and Eom described in the discussion of claim 9 out of a same material as the second insulating layer disclosed by Roh because the materials disclosed for the second insulating layer are also capable of functioning as insulators and it would have been a simple substitution of one element for another.
Regarding claim 13, the combination of Roh, Oh, and Eom described in the discussion of claim 9 further teaches “The display device of claim 12, wherein the pixel includes: a light emitting element” (Roh [0100-0101]; Fig. 2A, organic layer EL); “a transistor electrically connected to the light emitting element” (Roh [0076]: “The semiconductor layer 105 may form the channel of a thin-film transistor (“TFT”).”, [0078], and [0082]; Fig. 2A, semiconductor layer 105, gate electrode GE, source electrode SE, and drain electrode DE; note that the transistor is connected to the organic layer EL through the connecting electrode CNE and the anode electrode ANO), “and including a semiconductor pattern” (Roh [0076]; Fig. 2A, semiconductor layer 105) “and a gate overlapping the semiconductor pattern” (Roh [0078]; Fig. 2A, gate electrode GE); “an upper electrode disposed on the gate” (Roh [0082]; Fig. 2A, note that the drain electrode DE overlaps the gate electrode GE); “and a plurality of conductive layers electrically connected to the transistor, disposed on the upper electrode, and disposed in mutually different layers” (Roh [0096] and [0098-0099]; Fig. 2A, note that the connecting electrode CNE and the anode electrode ANO are connected to the drain electrode DE and that the connecting electrode CNE is disposed in the second via layer VIA2 and the anode electrode ANO is disposed in the bank layer BANK), “and a portion, which is disposed under the conductive pattern, of the signal line and the gate or the upper electrode include a same material” (Roh [0078]: “The first conductive layer 120 may include… a gate signal wire GSL. In an exemplary embodiment, the first conductive layer 120 may include at least one metal including at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), for example.” and [0082]: “The third conductive layer 140 may include… a wire pad PAD. In an exemplary embodiment, the third conductive layer 140 may include at least one of Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu, for example.”; note that the lists of disclosed materials for the first and third conductive layers 120 and 140 in these paragraphs are identical, so that both can be made from the same material).
Regarding claim 14, the combination of Roh, Oh, and Eom described in the discussion of claim 9 further teaches “The display device of claim 13, wherein the lower conductive pattern and at least some conductive layers of the plurality of conductive layers include a same material” (Roh [0082]: “The third conductive layer 140 may include… a wire pad PAD.” and [0096]: “A fourth conductive layer 150 may be disposed on the first via layer VIA1. The fourth conductive layer 150 may include… a connecting electrode CNE… The fourth conductive layer 150 may include at least one of the aforementioned exemplary materials of the third conductive layer 140.”; note that this allows for the third and fourth conductive layers 140 and 150 to be made from the same material), but does not teach “and the conductive pattern and other conductive layers of the plurality of conductive layers, which are disposed on the at least some conductive layers, include a same material.”
Roh, on the other hand, teaches that the other electrodes may be made from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, or Cu (Roh [0078], [0079]: “The second conductive layer 130 may include at least one of the aforementioned exemplary materials of the first conductive material.”, [0082], and [0096]).
The conductive materials taught by Roh can be incorporated into the combined device of Roh and Eom described in the discussion of claim 9 by making all of the conductive layers and the anode electrode out of the same material, selected from the disclosed list. The combined device teaches “and the conductive pattern and other conductive layers of the plurality of conductive layers, which are disposed on the at least some conductive layers, include a same material” (Roh [0078-0079], [0082], and [0096]; Fig. 2A, note that the anode electrode ANO is made of the same conductive material as the third conductive layer 140, which includes the wire pad PAD).
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Fig. 2 of Kim, reproduced with annotations added by the examiner.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Roh and Oh in further view of Kim, Pub. No. US 2022/0328727, hereafter referred to as Kim.
Regarding claim 8, the combination of Roh and Eom described in the discussion of claim 1 teaches “The display device of claim 1” but does not teach “wherein the insulating pattern has a semi-circular shape, when viewed in a cross-sectional view.”
Kim, on the other hand, teaches a conductive pad disposed in a similar location (Kim [0052]; Figs. 1 and 2, pad area PA) disposed on an insulating substrate (Kim [0062]; Fig. 2, base substrate SUB) with semicircular protrusions (Kim [0081]; Fig. 2, note the semicircular shape of the protrusions SUB_PT) and a pad with similar protrusions (Kim [0081]; Fig. 2, pad electrode PE and protrusions PE_PT; note the semicircular shape of the protrusions PE_PT). Furthermore, Kim teaches the use of an adhesive member to bond the pad to a circuit board, and that the goal of the invention is to reduce instances of connection faults (Kim [0004]).
The semicircular protrusions of Kim can be incorporated into the combined device of Roh and Oh described in the discussion of claim 1 by making the second insulating layer 112b such that the portions of the second insulating layer under the mesh have a semicircular cross section. The combined device teaches “wherein the insulating pattern has a semi-circular shape, when viewed in a cross-sectional view” (Roh [0122]; Fig. 7, second insulating layer 112b; Kim [0081]; Fig. 2, base substrate SUB and protrusions SUB_PT; note that the second insulating layer 112b has a semicircular cross section in the combined device).
It would have been obvious to one of ordinary skill in the art to have made the second insulating layer of the combined device of Roh and Oh such that it had a semicircular cross section because doing so would increase the surface area of the second insulating layer without changing the volume, improving adhesion between the lower portion of the mesh and the second insulating layer and it would be a simple substitution of one element for another.
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Reproduction of Figs. 1 and 2 of Hiroshige.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Roh in view of Oh and Hiroshige, Pub. No. JP 2013127658A, hereafter referred to as Hiroshige.
Regarding claim 19, Roh teaches “A method for manufacturing a display device” (Roh [0063]; Fig. 1, display device 1), “the method comprising: providing a preliminary signal pad” (Roh [0106]; Fig. 3, wire pads PAD; also see [0122] and Fig. 7, power pad PW_PAD1) “including an insulating pattern” (Roh [0079] and [0122]; Fig. 7, second insulating layer 112b); and “depositing a preliminary conductive pattern on the preliminary signal pad” (Roh [0122]; Fig. 7, power pad PW_PAD1); but does not teach “and patterning the preliminary conductive pattern to form a conductive pattern at least partially including a mesh pattern, wherein at least a portion of the mesh pattern is disposed on the insulating pattern.”
Oh, on the other hand, teaches a pad (Oh [0056]; Fig. 6, pad part 230) composed of a mesh (Oh [0056]; Fig. 6, pad 233) with a border (Oh [0056]; outline 236). In addition, Oh teaches that forming the pad as a mesh would help to alleviate the possibility of a metal pad being disconnected from a fine connecting wire during an etching process (Oh [0006]: “However, since fine line widths, such as those of the conductive lines, require an etching rate different from that used in the formation of a pad formed of a metal, the conductive lines of electrodes disposed on the periphery of the pads may be disconnected.”)
The pads with mesh patterns of Oh can be incorporated into the device of Roh by making the pads in the device of Roh with a mesh pattern. The combined device teaches “…a conductive pattern at least partially including a mesh pattern, wherein at least a portion of the mesh pattern is disposed on the insulating pattern.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use pads consisting of a mesh with a border as taught by Oh in the device of Roh because doing so would alleviate the possibility of the pad being disconnected from the connecting wire during an etching process (Oh [0006]) and it would be a simple substitution of one element for another.
The combination of Roh and Oh just described, however, does not teach “and patterning the preliminary conductive pattern to form a conductive pattern at least partially including a mesh pattern, wherein at least a portion of the mesh pattern is disposed on the insulating pattern.”
Hiroshige, on the other hand, teaches a method of forming a mesh for a touch screen (Hiroshige [0008]: “This invention was made in consideration of these problems, and aims to provide a conductive sheet and a touch panel that do not impair visibility near the electrode terminals in the sensing area.” and [0010]: “Preferably, the conductive sheet of the present invention has an electrode pattern that is a mesh shape made up of a grid…”; Figs. 1 and 2) in which a photoresist is formed and developed, followed by etching of a copper foil to form the mesh pattern (Hiroshige [0060]: “Alternatively, the first electrode pattern 16A and the second electrode pattern 16B may be formed by exposing and developing the photoresist film on the copper foil formed on the first transparent substrate 14A and the second transparent substrate 14B to form a resist pattern, and then etching the copper foil exposed from the resist pattern.”), i.e., formation of the device using photolithography.
The process of forming a mesh taught by Hiroshige can be incorporated into the combination of Roh and Oh through the use of photolithography to form the mesh pattern. The combined process teaches “and patterning the preliminary conductive pattern to form a conductive pattern at least partially including a mesh pattern, wherein at least a portion of the mesh pattern is disposed on the insulating pattern.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to form the mesh pattern of the combination of Roh and Oh using photolithography as taught by Hiroshige because using such a process allows the formation of finer details, as is required to form a mesh, and it would be a simple combination of elements of the two disclosures.
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Reproduction of Fig. 1.3 of Lin.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Roh, Oh, and Hiroshige in further view of Lin, B. J. et. al., Optical lithography: here is why, hereafter referred to as Lin.
Regarding claim 20, the combination of Roh, Oh, and Hiroshige described in the discussion of claim 19 teaches “The method of claim 19, wherein the patterning of the preliminary conductive pattern includes: forming a photoresist pattern on the preliminary conductive pattern” (Hiroshige [0060]); and “etching a portion of the preliminary conductive pattern exposed from the photoresist pattern” (Hiroshige [0060]); but does not explicitly teach “and removing the photoresist pattern to form a signal pad.”
Lin, on the other hand, teaches a typical photolithography process, which includes a step of removing the photoresist after etching the material underneath (Lin Fig. 1.3, note that the “Resist and ARC stripping” step follows the “Pattern transfer: Etch, lift-off, implant” step).
The step of removing the photoresist taught by Lin can be incorporated into the combined process of Roh, Oh, and Hiroshige described in the discussion of claim 19 by incorporating a step of removing the photoresist after etching the conductive pattern. The combined process teaches “and removing the photoresist pattern to form a signal pad” (Lin Fig. 1.3, “Resist and ARC stripping” step).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a step of removing the photoresist after etching the conductive pattern as taught by Lin in the combined process of Roh, Oh, and Hiroshige because doing so would allow for further connections between the mesh and other components to be formed and it would be a simple combination of elements of the two disclosures.
Conclusion
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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