DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 14 recites “the inclined surface of the step”. It is not clear, from this limitation, whether “the inclined surface of the step” is the same as “an inclined surface, which is a side surface of the impurity element implantation region in contact with the step” or is intended to be a different inclined surface. This issue renders the claim indefinite.
Claim 2, line 2 recites “an inclined surface”. It is not clear, from this limitation, whether this inclined surface is the same as “an inclined surface” of claim 1, from which this claim depends, or is a different inclined surface. This issue renders the claim indefinite.
Claim 3, line 2-3 recites “the inclined surface”. It is not clear, from this limitation, which inclined surface of claims 2-3 this is intended to refer to. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAKEUCHI (US 20140145212).
Regarding claim 1, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses a method of manufacturing a silicon carbide semiconductor device (the method shown in fig 11-12 of making the device in fig 10, see para 55-57) including an active region (the region R1 of the device to the left of 16 in fig 10 including the gate 41, see para 115) and a termination region (the region R2 including the recesses 16 and 17 which surrounds R1, see fig 10-12 and para 75) surrounding the active region, the method comprising:
performing ion implantation of forming an impurity element implantation region by ion- implanting an impurity element of a first conductivity type (n-type region 4 can be formed by ion implanting N-type impurities in to 3, see fig 11A, para 152) into a surface of a base region of a second conductivity type (p-type region 3, see fig 11A, para 152) provided above a drift layer of the first conductivity type (3 is above n-type drift layer 2, see fig 11A); and
performing etching (the etching steps that form recesses 16 and 17 and also the gate trench 6, see fig 12B and 12C, para 131 and 133) of forming a step in the termination region (the recesses 16 and 17 form a step, see fig 10 and 12C, para 131) and a trench in the active region (the trench 6 in which 40 and 41 are formed, see fig 10 and 12C, para 133), the etching including: removing a semiconductor layer including the impurity element implantation region of the termination region (16 and 17 are formed at least partially by removing 4, see fig 12B, para 131); and removing a semiconductor layer including the impurity element implantation region of the active region (the portion of 5 removed to make 6 includes part of 4, see fig 12C, para 133),
wherein, in the etching, an inclined surface, which is a side surface of the impurity element implantation region in contact with the step (the inclined side surface of 4 that borders 6, see fig 12B), is formed asymmetrically with a side surface of the impurity element implantation region in contact with the trench (the vertical side surface of 4 that borders the trench, see fig 12C), and
the inclined surface of the step of the termination region is more inclined than the side surface of the trench (the side surface of 4 in 16 is more inclined from the vertical than the side surface of 6, see fig 12C).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses the method according to claim 1, wherein in the etching, an inclined surface having a lower end that is connected to a flat portion that is a bottom surface of the step is formed by etching of the termination region (recesses 16 and 17 have an inclined side surface that is at least indirectly connected to the flat bottom surface of 17, see fig 12C).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses the method according to claim 2, further comprising forming a junction termination extension region of a second conductivity type from the lower end of the inclined surface toward an outer edge portion (p-type region 20 extends from a side surface of 17 towards the outer side of 2, see fig 10, para 77).
Regarding claim 5, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses the method according to claim 1, wherein in the ion implantation, the impurity element is ion-implanted into an entire surface of the base region (4 is formed along an entire top surface of 3, see fig 11A).
Regarding claim 6, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses the method according to claim 1, wherein in the etching, a depth of the step (a depth of the recess 16 and 17 is different from the depth of 6, see fig 12C) is set to be different from a depth of the trench.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKEUCHI (US 20140145212) in view of HIYOSHI (US 20130099251).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI discloses the method according to claim 1.
TAKEUCHI fails to explicitly disclose, further comprising performing second ion implantation of forming a second impurity element implantation region by ion-implanting a second impurity element of a second conductivity type into the surface of the base region,
wherein in an overlapping portion where the second impurity element implantation region overlaps the impurity element implantation region, the second impurity element includes an impurity density higher than an impurity density of the impurity element.
HIYOSHI teaches the method according to claim 1, further comprising performing second ion implantation (the ion implantation to form 5, see fig 6, para 53-54) of forming a second impurity element implantation region (fig 6, 5, para 53) by ion-implanting a second impurity element of a second conductivity type (5 is a p-type region, see para 53 and 33) into the surface of the base region,
wherein in an overlapping portion where the second impurity element implantation region overlaps the impurity element implantation region, the second impurity element includes an impurity density higher than an impurity density of the impurity element (5 is a p-type region, so the p-dopant density must be higher, see fig 6, para 33).
TAKEUSHI and HIYOSHI are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TAKEUCHI with the overlapping doped portions of HIYOSHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TAKEUCHI with the overlapping doped portions of HIYOSHI in order to improve carrier mobility (see HIYOSHI para 63).
Regarding claim 9, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI and HIYOSHI disclose the method according to claim 7.
TAKEUCHI further discloses, wherein the second impurity element implantation region is deeper than the impurity element implantation region (18 is deeper than 4, see fig 10).
Regarding claim 13, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI and HIYOSHI disclose the method according to claim 7.
TAKEUCHI fails to explicitly disclose a method, further comprising forming a metal-containing layer containing metal and being in contact with the impurity element implantation region and the overlapping portion, and
wherein at least a part of a bottom surface of the overlapping portion, along with the base region, configures a part of a semiconductor region of a second conductivity type in contact with the drift layer on a side below the trench.
HIYOSHI teaches the method according to claim 7 a method, further comprising forming a metal-containing layer containing metal and being in contact with the impurity element implantation region and the overlapping portion (conductor film 12 which can be a metal, is formed in contact with 4 and 5, see fig 2, para 56 and 58), and
wherein at least a part of a bottom surface of the overlapping portion, along with the base region, configures a part of a semiconductor region of a second conductivity type in contact with the drift layer on a side below the trench (5 and 3 form a p-type region that is in contact with 2, see fig 2, para 33).
TAKEUSHI and HIYOSHI are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TAKEUCHI with the overlapping doped portions of HIYOSHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TAKEUCHI with the overlapping doped portions of HIYOSHI in order to improve carrier mobility (see HIYOSHI para 63).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKEUCHI (US 20140145212) in view of HIYOSHI (US 20130099251) and further in view of WADA (US 20160181372).
Regarding claim 8, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI and HIYOSHI disclose the method according to claim 7.
TAKEUCHI and HIYOSHI fail to explicitly disclose a method, wherein, in the overlapping portion, the second impurity element includes an impurity density that is at least two times as high as an impurity density of the impurity element.
WADA teaches a method, wherein, in the overlapping portion, the second impurity element includes an impurity density that is at least two times as high as an impurity density of the impurity element (p+ second impurity element region 84 can be doped to 1E20 per cc and the n impurity element region 83 can be 2E19 per cc, see fig 1, para 53-54).
TAKEUCHI, HIYOSHI and WADA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TAKEUCHI and HIYOSHI with the specific doping density of WADA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TAKEUCHI and HIYOSHI with the specific doping density of WADA in order to improve breakdown voltage (see WADA para 32).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKEUCHI (US 20140145212) in view of HIYOSHI (US 20130099251) and further in view of MATSUKI (US 20160133741).
Regarding claim 10, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI and HIYOSHI disclose the method according to claim 7.
TAKEUCHI and HIYOSHI fail to explicitly disclose a method, further comprising forming an interlayer insulating film that covers at least a part of the overlapping portion and continues to the step in the termination region.
MATSUKI teaches a method, further comprising forming an interlayer insulating film (fig 4C, 12, para 79) that covers at least a part of the overlapping portion and continues to the step in the termination region (12 covers 5 and also extends to cover the step, see fig 4C, para 79).
TAKEUCHI, HIYOSHI and MATSUKI are analogous art because they both are directed towards methods of making semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TAKEUCHI and HIYOSHI with the interlayer insulating film of MATSUKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TAKEUCHI and HIYOSHI with the interlayer insulating film of MATSUKI in order to form a high-breakdown device (see MATSUKI para 57).
Regarding claim 11, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI, MATSUKI and HIYOSHI disclose the method according to claim 10.
TAKEUCHI fails to explicitly disclose a method, wherein the active region is provided with a protection region of a second conductivity type in contact with a bottom of the trench, and
wherein the termination region is provided with a relaxation region of a second conductivity type facing the protection region in a horizontal direction.
HIYOSHI teaches a method, wherein the active region is provided with a protection region of a second conductivity type in contact with a bottom of the trench (fig 2, 7, para 33), and
wherein the termination region is provided with a relaxation region of a second conductivity type facing the protection region in a horizontal direction (21 faces 7 in a horizontal direction, see fig 2, 21, para 34).
TAKEUCHI, MATSUKI and HIYOSHI are analogous art because they both are directed towards method of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of TAKEUCHI with the protection or relaxation region of HIYOSHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of TAKEUCHI with the protection or relaxation region of HIYOSHI in order to improve carrier mobility (see HIYOSHI para 63).
Regarding claim 12, as best as the examiner is able to ascertain the claimed invention, TAKEUCHI, MATSUKI and HIYOSHI disclose the method according to claim 11.
TAKEUCHI fails to explicitly disclose a method, wherein the relaxation region faces the interlayer insulating film in a depth direction and extends from the step side toward the active region side in the horizontal direction.
HIYOSHI teaches a method, wherein the relaxation region faces the interlayer insulating film in a depth direction (21 has a surface which faces upwards towards insulating layers 8C and 10, see fig 2, para 37) and extends from the step side toward the active region side in the horizontal direction (21 extends from ST towards CL, see fig 2).
TAKEUCHI, MATSUKI and HIYOSHI are analogous art because they both are directed towards method of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of TAKEUCHI with the protection or relaxation region of HIYOSHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of TAKEUCHI with the protection or relaxation region of HIYOSHI in order to improve carrier mobility (see HIYOSHI para 63).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights