DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 2/6/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HIYOSHI (US 20130099251).
Regarding claim 1, HIYOSHI discloses a method of manufacturing a silicon carbide semiconductor device including an active region and a termination region surrounding the active region, the method comprising:
performing ion implantation (the ion implantation that forms n-type source contact layer 4, see fig 3, para 43-44) of forming an impurity element implantation region (4, see fig 3, para 43-44) by ion- implanting an impurity element of a first conductivity type (the n-type impurity that is implanted to form 4, see fig 3, para 43-44) into a surface of a base region (the top surface of the base region 3, see fig 3, para 43-44) of a second conductivity type (the p-type region 3, see fig 3, para 44) provided above a drift layer of the first conductivity type (n-type layer 2, see fig 3, para 43-44); and
performing etching (the etching done in fig 4-5, see para 43-52) of forming a step in the termination region (the step St of the terrace 6T, see fig 5, para 26) and a trench in the active region (the trench 6C, see fig 5, para 26), the etching including: removing a semiconductor layer including the impurity element implantation region of the termination region; and removing a semiconductor layer including the impurity element implantation region of the active region (portions of the n-type layer 4 are removed in both the active region CL and the termination region TM, see fig 5, para 24).
Regarding claim 2, HIYOSHI discloses the method according to claim 1, wherein in the etching, an inclined surface whose lower end is connected to a flat portion that is a bottom surface of the step is formed by etching of the termination region (the sidewall ST is inclined in TM and meets bottom surface BT, see fig 5, para 24).
Regarding claim 3, HIYOSHI discloses the method according to claim 2, further comprising forming a junction termination extension region of a second conductivity type from the lower end of the inclined surface toward an outer edge portion (p-type JTE region 21 is formed at the lower end of ST, see fig 2 and 6, para 34).
Regarding claim 4, HIYOSHI discloses the method according to claim 1, wherein, in the etching, an inclined surface, which is a side surface of the impurity element implantation region in contact with the step (the portion of ST which is the side surface of 4 in 6T, see fig 6, para 47), is formed asymmetrically with a side surface of the impurity element implantation region in contact with the trench (the right surface of 4 in 6T is laterally asymmetric with the right surface of 4 in 6C in region CL, see fig 5, para 47).
Regarding claim 5, HIYOSHI discloses the method according to claim 1, wherein in the ion implantation, the impurity element is ion-implanted into an entire surface of the base region (4 is formed on the entire surface TS, see fig 3, para 43).
Regarding claim 7, HIYOSHI discloses the method according to claim 1, further comprising performing second ion implantation (the ion implantation to form 5, see fig 6, para 53-54) of forming a second impurity element implantation region (fig 6, 5, para 53) by ion-implanting a second impurity element of a second conductivity type (5 is a p-type region, see para 53 and 33) into the surface of the base region,
wherein in an overlapping portion where the second impurity element implantation region overlaps the impurity element implantation region, the second impurity element includes an impurity density higher than an impurity density of the impurity element (5 is a p-type region, so the p-dopant density must be higher, see fig 6, para 33).
Regarding claim 13, HIYOSHI discloses the method according to claim 7, further comprising forming a metal-containing layer containing metal and being in contact with the impurity element implantation region and the overlapping portion (conductor film 12 which can be a metal, is formed in contact with 4 and 5, see fig 2, para 56 and 58), and
wherein at least a part of a bottom surface of the overlapping portion, along with the base region, configures a part of a semiconductor region of a second conductivity type in contact with the drift layer on a side below the trench (5 and 3 form a p-type region that is in contact with 2, see fig 2, para 33).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIYOSHI (US 20130099251) in view of MASUDA (US 20160293690).
Regarding claim 6, HIYOSHI discloses the method according to claim 1.
HIYOSHI fails to explicitly disclose a method, wherein in the etching, a depth of the step is set to be different from a depth of the trench.
MASUDA teaches a method wherein in the etching, a depth of the step is set to be different from a depth of the trench (bottom surface of the step PT is at a different depth than bottom surface of the trench BT, see fig 14, para 54).
HIYOSHI and MASUDA are analogous art because they both are directed towards methods of making trench gate transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of HIYOSHI with the etching depths of MASUDA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of HIYOSHI with the etching depths of MASUDA in order to increase the breakdown voltage (see MASUDA para 25).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIYOSHI (US 20130099251) in view of WADA (US 20160181381).
Regarding claim 8, HIYOSHI discloses the method according to claim 7.
HIYOSHI fails to explicitly disclose a method, wherein, in the overlapping portion, the second impurity element includes an impurity density that is at least two times as high as an impurity density of the impurity element.
WADA teaches a method, wherein, in the overlapping portion, the second impurity element includes an impurity density that is at least two times as high as an impurity density of the impurity element (p+ second impurity element region 84 can be doped to 1E20 per cc and the n impurity element region 83 can be 2E19 per cc, see fig 1, para 53-54).
HIYOSHI and WADA are analogous art because they both are directed towards methods of making trench gate transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of HIYOSHI with the impurity density of WADA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of HIYOSHI with the impurity density of WADA in order to improve breakdown voltage (see WADA para 32).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIYOSHI (US 20130099251) in view of KUMADA (US 20200020800).
Regarding claim 9, HIYOSHI discloses the method according to claim 7.
HIYOSHI fails to explicitly disclose a method, wherein the second impurity element implantation region is deeper than the impurity element implantation region.
KUMADA teaches a method, wherein the second impurity element implantation region is deeper than the impurity element implantation region (second impurity region 16 extends deeper that impurity region 15, see fig 6, para 81).
HIYOSHI and KUMADA are analogous art because they both are directed towards methods of making transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of HIYOSHI with the impurity region shape of KUMADA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of HIYOSHI with the impurity region shape of KUMADA in order to increase the breakdown voltage (see KUMADA para 79).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over HIYOSHI (US 20130099251) in view of MATSUKI (US 20160133741).
Regarding claim 10, HIYOSHI discloses the method according to claim 7.
HIYOSHI fails to explicitly disclose a method, further comprising forming an interlayer insulating film that covers at least a part of the overlapping portion and continues to the step in the termination region.
MATSUKI teaches a method, further comprising forming an interlayer insulating film (fig 4C, 12, para 79) that covers at least a part of the overlapping portion and continues to the step in the termination region (12 covers 5 and also extends to cover the step, see fig 4C, para 79).
HIYOSHI and MATSUKI are analogous art because they both are directed towards methods of making vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of HIYOSHI with the interlayer insulating film of MATSUKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of HIYOSHI with the interlayer insulating film of MATSUKI in order to form a high-breakdown device (see MATSUKI para 57).
Regarding claim 11, HIYOSHI and MATSUKI disclose the method according to claim 10.
HIYOSHI further discloses a method, wherein the active region is provided with a protection region of a second conductivity type in contact with a bottom of the trench (fig 2, 7, para 33), and
wherein the termination region is provided with a relaxation region of a second conductivity type facing the protection region in a horizontal direction (21 faces 7 in a horizontal direction, see fig 2, 21, para 34).
Regarding claim 12, HIYOSHI and MATSUKI disclose the method according to claim 11.
HIYOSHI further discloses a method, wherein the relaxation region faces the interlayer insulating film in a depth direction (21 has a surface which faces upwards towards insulating layers 8C and 10, see fig 2, para 37) and extends from the step side toward the active region side in the horizontal direction (21 extends from ST towards CL, see fig 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811