Detailed Action
Claims 1-14 are presently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 1, the claim recites “An information processing apparatus comprising: search condition specification processor circuitry … input data specification processor circuitry.” However, nowhere in the specification explicitly recites ‘search condition specification processor circuitry’ and ‘input data specification processor circuitry’. The specification paragraph [0044] recites a search condition specification processing unit 112 and an input data specification processing unit 113 which are distinguishable from ‘processor circuitry’. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Regarding Claim 2, the claim recites ‘the search condition specification processor circuitry’ and ‘branch condition storage processor circuitry’. Regarding ‘the search condition specification processor circuitry’, the claim is rejected for at least the same reasons as claim 1. The specification paragraph [0014] recites a branch condition storage processing unit which is distinguishable from ‘processor circuitry’. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Regarding Claim 3, the claim recites ‘the input data specification processor circuitry’. The claim is rejected for at least the same reasons as claim 1
Regarding claim 4, the claim recites ‘the search condition specification processor circuitry’, ‘sorting processor circuitry’, and ‘the input data specification processor circuitry’. Regarding ‘the search condition specification processor circuitry’ and ‘the input data specification processor circuitry’, the claim is rejected for at least the same reasons as claim 1. Regarding ‘sorting processor circuitry’, the nowhere in the specification explicitly recites the sorting processor circuitry. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Regarding Claim 5, the claim recites ‘variable setting processor circuitry’. Nowhere in the specification explicitly disclose the processor circuitry and the spec fails to disclose sufficient structure for performing the entire claimed function. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Regarding Claim 6, the claim recites “target output data setting processor circuitry.” The specification paragraph [0022] discloses ‘a target output data setting unit’ which is distinguishable from ‘target output data setting processor circuitry’ and the spec fails to disclose sufficient structure for performing the entire claimed functions. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Regarding Claim 7, the claim recites ‘wherein the input data specification processor circuitry’ and ‘condition determination processor circuitry’. Regarding ‘wherein the input data specification processor circuitry’, the claim is rejected for at least the same reasons as claim 1. Regarding ‘condition determination processor circuitry’, the spec [0024] discloses ‘a condition determination unit’ which is distinguishable from ‘condition determination processor circuitry’ and the spec fails to disclose sufficient structure for performing the entire claimed functions. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Claim 8 depends from claim 1 and inherits all its limitations. Therefore, claim 8 is rejected under the same reasons.
Regarding Claim 9, the claim recites ‘the search condition specification processor circuitry’ and ‘branch condition integration processor circuitry’. Regarding ‘the search condition specification processor circuitry’, the claim is rejected for at least the same reasons as claim 1. Regarding ‘branch condition integration processor circuitry’, the spec paragraph [0028] recites ‘include a branch condition integration processing unit’ which is distinguishable from ‘branch condition integration processor circuitry’ and the spec fails to disclose sufficient structure for performing the entire claimed functions. Accordingly, examiner concluded that the claim fails to comply with the written description requirement.
Claims 10-11 depend from claim 1 and inherit all its limitations. Therefore, claims 10-11 are rejected under the same reasons.
Claim 14 is a system claim which recites the same feature as the apparatus claim 1, and is rejected for at least the same reasons.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “The information processing apparatus according to claim 1, further comprising: variable setting processor circuitry that performs setting regarding manipulability of a variable.” It is unclear which variable does “a variable” refers to, because Claim 1 also recites “a manipulable variable”.
For purpose of the examination, the examiner interprets the limitation to mean: “The information processing apparatus according to claim 1, further comprising: variable setting processor circuitry that performs setting regarding manipulability of the manipulable variable.”
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1,
Step 1: Claim 1 recites an information processing apparatus comprising: search condition specification processor circuitry and input data specification processor circuitry. Therefore, it is directed to the statutory category of a machine.
2A Prong 1:
2A Prong 2:
An information processing apparatus comprising: search condition specification processor circuitry; and input data specification processor circuitry (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
The additional elements as disclosed above alone or in combination do not integrate the judicial exception into practical application as they are mere generic computer functions that are implemented to perform the disclosed abstract idea above.
2B:
An information processing apparatus comprising: search condition specification processor circuitry; and input data specification processor circuitry (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
The additional elements as disclosed above in combination of the abstract idea are not sufficient to amount to significantly more than the judicial exception as they are generic computer functions that are implemented to perform the disclosed abstract idea above.
Regarding Claim 2,
Step 1: A machine, as above.
2A Prong 1:
2A Prong 2: The information processing apparatus according to claim 1, wherein the search condition specification processor circuitry further comprises: branch condition storage processor circuitry that performs (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
and performs processing of storing the branch condition in a case where a branch condition related to a manipulable variable is associated with the node. (insignificant extra-solution activity of mere data gathering MPEP 2106.05(g)(iii))
2B: The information processing apparatus according to claim 1, wherein the search condition specification processor circuitry further comprises: branch condition storage processor circuitry that performs (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
and performs processing of storing the branch condition in a case where a branch condition related to a manipulable variable is associated with the node. (indicated as the insignificant extra-solution activity MPEP 2106.05(g) in Step 2A Prong 2. Therefore, it is re-evaluated as well understood, routine and conventional activity MPEP 2106.05(d)(II)(iv) of storing and retrieving information in memory)
Regarding Claim 3,
Step 1: A machine, as above.
2A Prong 1: … and specify temporary input data for which output data of the tree structure model corresponding to the temporary input data becomes the target output data or becomes closest to the target output data as the input data among the temporary input data. (mental process of judgment – predict which output data is to be generated, which can be done in the human mind)
2A Prong 2: The information processing apparatus according to claim 1, (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
wherein the input data specification processor circuitry inputs one or a plurality of pieces of temporary input data that satisfy the search condition to the tree structure model (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
wherein the input data specification processor circuitry inputs one or a plurality of pieces of temporary input data that satisfy the search condition to the tree structure model (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 4,
Step 1: A machine, as above.
2A Prong 1:
2A Prong 2: The information processing apparatus according to claim 1, wherein the search condition specification processor circuitry further comprises sorting processor circuitry that (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
the input data specification processor circuitry (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, wherein the search condition specification processor circuitry further comprises sorting processor circuitry that (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
the input data specification processor circuitry (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 5,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, further comprising: variable setting processor circuitry that performs setting regarding manipulability of a variable. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, further comprising: variable setting processor circuitry that performs setting regarding manipulability of a variable. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 6,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, further comprising: target output data setting processor circuitry that sets content of the target output data. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, further comprising: target output data setting processor circuitry that sets content of the target output data. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 7,
Step 1: A machine, as above.
2A Prong 1:
2A Prong 2: The information processing apparatus according to claim 1, wherein the input data specification processor circuitry further comprises: condition determination processor circuitry that (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, wherein the input data specification processor circuitry further comprises: condition determination processor circuitry that (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 8,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, wherein there are a plurality of pieces of the input data. (a field of use and technological environment MPEP 2106.05(h))
2B: The information processing apparatus according to claim 1, wherein there are a plurality of pieces of the input data. (a field of use and technological environment MPEP 2106.05(h))
Regarding Claim 9,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, wherein there are a plurality of the tree structure models, and the search condition specification processor circuitry further comprises branch condition integration processor circuitry that generates the search condition by integrating the branch conditions. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, wherein there are a plurality of the tree structure models, and the search condition specification processor circuitry further comprises branch condition integration processor circuitry that generates the search condition by integrating the branch conditions. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 10,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, wherein the tree structure is a learned decision tree. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: The information processing apparatus according to claim 1, wherein the tree structure is a learned decision tree. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Regarding Claim 11,
Step 1: A machine, as above.
2A Prong 1: Incorporates the rejection of claim 1.
2A Prong 2: The information processing apparatus according to claim 1, wherein the plurality of tree structure models is obtained through ensemble learning. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f) – recites generic machine learning model training process)
2B: The information processing apparatus according to claim 1, wherein the plurality of tree structure models is obtained through ensemble learning. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f) – recites generic machine learning model training process)
Regarding Claim 12,
Step 1: Claim 12 recites an information processing method. Therefore, it is directed to the statutory category of Processes.
2A Prong 1: An information processing method comprising: specifying a search condition on a basis of a branch condition associated with each node of one or a plurality of tree structure models and related to a manipulable variable; and (mental process of evaluation – determining a search condition based on the branch condition, which can be performed with the aid of pen and paper)
specifying input data from which target output data or output data close to the target output data is to be generated in the tree structure model on a basis of the search condition. (mental process of judgment – predict which output data is to be generated, which can be done in the human mind)
2A Prong 2: This judicial exception is not integrated into a practical application.
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Regarding Claim 13,
Step 1: Processes, as above.
2A Prong 1: Incorporates the rejection of claim 12.
2A Prong 2: A non-transitory computer readable storage medium encoded with computer readable instructions, which, when executed by processor circuitry, cause the processor circuitry to perform the information processing method according to claim 12. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
2B: A non-transitory computer readable storage medium encoded with computer readable instructions, which, when executed by processor circuitry, cause the processor circuitry to perform the information processing method according to claim 12. (mere instructions to apply an exception using a generic computer component MPEP 2106.05(f))
Claim 14 is a system claim which recites the same feature as the apparatus claim 1, and is rejected for at least the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-8, 10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakanoya (US 20210012214 A1).
Regarding Claim 1, Nakanoya teaches:
An information processing apparatus comprising: ([0095] shows that the division condition is associated with each node of a decision tree structure and processes input learning data. [0071]-[0072] and [0112]-[0113] shows that the learning apparatus includes processors and memories)
search condition specification processor circuitry that specifies a search condition on a basis of a branch condition associated with each node of one or a plurality of tree structure models and related to a manipulable variable; and ([0095] shows that the division condition is associated with each node of a decision tree structure. [0101] In step A2, the division condition generation unit 12 (i.e., search condition specification processor circuitry) generates (specifies) the division condition (i.e., search condition) in accordance with the feature amount in the learning data and the requirement of the designated division condition (i.e., branch condition), and then the learning data division unit 13 divides the learning data in accordance with the division condition. [0027] indicates that the division conditions are manipulable variables)
input data specification processor circuitry that specifies input data from which target output data or output data close to the target output data is to be generated in the tree structure model on a basis of the search condition. ([0095] shows that the division condition is associated with each node of a decision tree structure. [0102]-[0103] discloses that in step A4 and step A5, the learning data evaluation unit 14 (i.e., input data specification processor circuitry) determines (specifies) whether the divided learning data is statistically significantly different from the predicted values based on the difference between the pre-division and post-division groups)
Regarding Claim 2, Nakanoya teaches:
The information processing apparatus according to claim 1,
wherein the search condition specification processor circuitry further comprises:
branch condition storage processor circuitry that performs determination processing regarding the branch condition for each node of the tree structure model and performs processing of storing the branch condition in a case where a branch condition related to a manipulable variable is associated with the node. ([0071]-[0072] and [0112]-[0113] shows that the learning apparatus includes processors and memories. [0163]-[0175] indicates that the program that applies branch condition for each node of the decision tree to perform the division of the input data is recorded in the computer-readable recording medium)
Regarding Claim 3, Nakanoya teaches:
The information processing apparatus according to claim 1,
wherein the input data specification processor circuitry inputs one or a plurality of pieces of temporary input data that satisfy the search condition to the tree structure model and specify temporary input data for which output data of the tree structure model corresponding to the temporary input data becomes the target output data or becomes closest to the target output data as the input data among the temporary input data. ([0086] The learning data evaluation unit 14 first evaluate the input data (pre-division groups) using the post-division groups (i.e., target output data). The ‘groups’ indicates that there are plurality of pieces of temporary input data. If satisfies the statistical condition, [0090] updates the division condition and then [0092] the division unit 13 and the evaluation unit 14 performs the division and evaluation on the data. [0095] The node generation unit sends the groups divided with the division condition of the node to the division condition generation unit 12. The division condition generation unit 12 continues the above-described processing taking the received groups as new-pre-division groups. [0096] If the division condition is not detected, the node generation unit 15 sets those groups to the lowermost layer node of the decision tree)
Regarding Claim 5, Nakanoya teaches:
The information processing apparatus according to claim 1, further comprising: variable setting processor circuitry that performs setting regarding manipulability of a variable. ([0027]-[0030] discloses how the apparatus sets the variable (parameters) of the decision tree)
Regarding Claim 6, Nakanoya teaches:
The information processing apparatus according to claim 1, further comprising: target output data setting processor circuitry that sets content of the target output data. ([0071]-[0072] and [0112]-[0113] shows that the learning apparatus includes processors and memories. [0087] discloses generating two post-division groups and one pre-division group for the evaluation disclosed in paragraphs [0102]-[0103])
Regarding Claim 7, Nakanoya teaches:
The information processing apparatus according to claim 1, wherein the input data specification processor circuitry further comprises: condition determination processor circuitry that determines whether or not the specified input data satisfies a predetermined condition. ([0055] and [0102]-[0103] discloses that in step A4 and step A5, the learning data evaluation unit 14 (i.e., input data specification processor circuitry) determines (specifies) whether the divided learning data is statistically significantly different from the predicted values based on the difference (i.e., the predetermined condition) between the pre-division and post-division groups)
Regarding Claim 8, Nakanoya teaches:
The information processing apparatus according to claim 1,
wherein there are a plurality of pieces of the input data. ([0095] shows that the division condition is associated with each node of a decision tree structure. [0102]-[0103] discloses that in step A4 and step A5, the learning data evaluation unit 14 (i.e., input data specification processor circuitry) determines (specifies) whether the divided learning data is statistically significantly different from the predicted values based on the difference between the pre-division and post-division groups. The word ‘groups’ indicates that there are a plurality of pieces of the input learning data)
Regarding Claim 10, Nakanoya teaches:
The information processing apparatus according to claim 1,
wherein the tree structure is a learned decision tree. ([0095] shows that the division condition is associated with each node of a decision tree structure and processes input learning data)
Regarding Claim 12, Nakanoya teaches:
An information processing method comprising: ([0095] shows that the division condition is associated with each node of a decision tree structure and processes input learning data. [0071]-[0072] and [0112]-[0113] shows that the learning apparatus includes processors and memories)
specifying a search condition on a basis of a branch condition associated with each node of one or a plurality of tree structure models and related to a manipulable variable; and ([0095] shows that the division condition is associated with each node of a decision tree structure. [0101] In step A2, the division condition generation unit 12 (i.e., search condition specification processor circuitry) generates (specifies) the division condition (i.e., search condition) in accordance with the feature amount in the learning data and the requirement of the designated division condition (i.e., branch condition), and then the learning data division unit 13 divides the learning data in accordance with the division condition. [0027] indicates that the division conditions are manipulable variables)
specifying input data from which target output data or output data close to the target output data is to be generated in the tree structure model on a basis of the search condition. ([0095] shows that the division condition is associated with each node of a decision tree structure. [0102]-[0103] discloses that in step A4 and step A5, the learning data evaluation unit 14 (i.e., input data specification processor circuitry) determines (specifies) whether the divided learning data is statistically significantly different from the predicted values based on the difference between the pre-division and post-division groups)
Regarding Claim 13, Nakanoya teaches:
A non-transitory computer readable storage medium encoded with computer readable instructions, which, when executed by processor circuitry, cause the processor circuitry to perform the information processing method according to claim 12. ([0071]-[0072] and [0112]-[0113] shows that the learning apparatus includes processors and memories)
Claim 14 is a system claim which recites the same feature as the apparatus claim 1, and is rejected for at least the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakanoya in view of Tanaka et al. (US 20200143290 A1, hereinafter ‘Tanaka’).
Regarding Claim 4, Nakanoya teaches:
The information processing apparatus according to claim 1.
However, Nakanoya does not specifically disclose:
wherein the search condition specification processor circuitry further comprises sorting processor circuitry that sorts the branch conditions in accordance with a magnitude relationship and specifies the sorted branch conditions as a search condition, and
the input data specification processor circuitry specifies an arbitrary value between adjacent branch conditions in the search condition as the input data.
Tanaka teaches:
wherein the search condition specification processor circuitry further comprises sorting processor circuitry that sorts the branch conditions in accordance with a magnitude relationship and specifies the sorted branch conditions as a search condition, and ([Tanaka, 0337] The classification module 50 (i.e., sorting processor circuitry) determines the feature amount (i.e., a magnitude relationship) of the learning data, and determines whether to cause the read-out sample data to branch to the left side or to the right side of depth 1, node 1. The classification module 50 then rewrites the address of the learning data in ascending or descending order based on the determination)
the input data specification processor circuitry specifies an arbitrary value between adjacent branch conditions in the search condition as the input data. ([Tanaka, 0108] discloses how the learning algorithm treats the missing value. The threshold candidate (i.e., the arbitrary value) may be obtained, placed between the left node and the right node (i.e., between adjacent branch conditions, wherein each node refers to each branch condition), and may be assigned to any of the left node or the right node)
Before the effective filing date of the invention to a person of ordinary skill in the art, it would have been obvious, having the teachings of Nakanoya and Tanaka to use the method of sorting the branch conditions of an ensemble tree model in accordance with a magnitude relationship of Tanaka to implement the tree structure processing apparatus of Nakanoya. The suggestion and/or motivation to do so is to improve the performance of the apparatus, as arranging the branch conditions in the memory allows the system to perform the ensemble learning of random forest models in parallel [Tanaka, 0186].
Regarding Claim 9, Nakanoya teaches:
The information processing apparatus according to claim 1,
the search condition specification processor circuitry further comprises branch condition integration processor circuitry that generates the search condition by integrating the branch conditions. ([0073] discloses generating the search condition (i.e., division condition) using the division condition generation unit 12 (i.e., search condition specification processor circuitry) by integrating the feature amounts information and a complexity requirement that indicates the number of feature amounts (i.e., branch conditions))
However, Nakanoya does not specifically disclose:
wherein there are a plurality of the tree structure models.
Tanaka teaches:
wherein there are a plurality of the tree structure models. ([Tanaka, 0066] and [0081] shows that there are a plurality of decision trees)
Regarding Claim 11, Nakanoya in view of Tanaka teaches:
The information processing apparatus according to claim 1, wherein the plurality of tree structure models is obtained through ensemble learning. ([Tanaka, 0066] and [0081] shows that there are a plurality of decision trees and trained based on ensemble learning)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUN KWON whose telephone number is (571)272-2072. The examiner can normally be reached Monday – Friday 8:00AM – 5:00PM ET.
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/JUN KWON/Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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