DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 7, 2025 and February 12, 2026 are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with: (1) 37 CFR 1.84(p)(4) because:
reference character “113” has been used to designate both “the top electrode 113” and “the top conductive layer 113” in paragraph [0062]
reference character “108” has been used to designate “the top material layer 108” throughout the majority of the description, but also used to designate “the third material layer 108” multiple times throughout paragraphs [0075-0076]
and (2) 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
reference character
reference character “151T”, described in paragraph [0040] as “the top surface 151T”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. § 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-10 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. § 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the second support layer" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the claim has been interpreted by the Examiner according to FIGs. 4, 5, and paragraphs [0030-0036] as follows:
Claim 7: “The semiconductor device of claim 6, further comprising a middle support layer positioned between the bottom support layer and the top support layer, wherein the middle support layer is distant from both the bottom support layer and the top support layer, and laterally surrounds the bottom electrode.”
Claims 8, 9, and 10 all ultimately depend from Claim 7 and do not resolve the indefiniteness; therefore, they are rejected for the same reasons as Claim 7 due to their dependence therefrom.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. § 102 and § 103 (or as subject to pre-AIA 35 U.S.C. § 102 and § 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Zhao, US PGPub 2022/0059540 A1 (hereinafter referred to as Zhao), in view of Yoon et al., US Patent No. 9647056 B2 (hereinafter referred to as Yoon).
Regarding claim 1, Zhao discloses a semiconductor device (Zhao FIG. 1, paragraphs [0005-0006]), comprising:
a substrate (Zhao FIG. 1, element 1; paragraph [0046]);
a bottom electrode (lower electrode layer 33) positioned over the substrate and comprising a container-shaped profile (Zhao FIGs. 1, 3; paragraph [0058]); and
a top support layer (second insulating dielectric layer 324) overhung the substrate and attached to the bottom electrode (Zhao FIGs. 1, 15; paragraphs [0056-0057).
However, Zhao does not disclose wherein a thickness ratio of a thickness of the top support layer to a thickness of the bottom electrode is between about 3.0% and about 8.0%.
In analogous art, Yoon teaches a semiconductor device with a similar capacitor structure wherein a top support layer (Yoon, second supporting pattern 152) thickness ranges from 30-150nm (Yoon Col 8, lines 55-56) and a bottom electrode (Yoon, lower electrode 170) thickness is equal to at least the sum of the thicknesses of the layers in which the hole is formed wherein the electrode is deposited (see Yoon FIGs. 12, 15, elements 120, 121, 132 (130), 140, 141, and 152 (150)) and which is taught as follows: “the first mold layer 120 may be formed to a thickness of about 5000 Å-10000 Å” (Yoon Col 11, lines 19-21); “the first buffer layer 121 may be formed to a thickness of about 50 Å-200 Å” (Yoon Col 11, lines 41-43); “the first supporting layer 130 may be formed to a thickness of about 100 Å-500 Å” (Yoon Col 11, lines 62-64); “the second mold layer 140 may be formed to a thickness of about 5000 Å to 15000 Å” (Yoon Col 12, lines 48-50); “the second buffer layer 141 may be formed to a thickness of about 100 Å-500 Å” (Yoon Col 12, lines 66-67 to Col 13, line 1); and “the second supporting layer 150 may be formed to a thickness of about 300 Å-1500 Å” (Yoon Col 13, lines 26-27). In other words, Yoon teaches that the thickness of the bottom electrode (Yoon, the lower electrode 170) is at least 10500 Å-27700 Å. Hence, Yoon teaches a thickness ratio of a thickness of the top support layer (Yoon, second supporting layer 150/152, 300 Å-1500 Å) to a thickness of the bottom electrode (Yoon, lower electrode 170, 10500 Å-27700 Å) be between about 1.0% and about 14.0%.
While Yoon does not teach that the thickness ratio be explicitly about 3.0% to about 8.0%, the claimed range of the instant application is within the range taught by Yoon. From MPEP § 2144.05: “in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists” and “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” The CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). Yoon clearly discloses that the thickness of the top electrode (Yoon, lower electrode 170) is a result-effective variable, as “the capacitance of a capacitor is proportional to a surface area of the lower electrode 170” and therefore, to increase capacitance, “the lower electrode 170 may be formed to have an increased height. Accordingly, the lower electrode 170 may have an increased aspect ratio” (Yoon, Col 7, lines 57-61), where “height”, in reference to the lower electrode 170, as taught by Yoon is synonymous with “thickness”, in reference to the bottom electrode, as disclosed in the instant application.
As the thickness of the top electrode is a recognized result-effective variable and Yoon further teaches that to support such increased height, additional support layers can be used (Yoon, Col 8, lines 6-8), it would have been obvious to a person of ordinary skill in the art that, when increasing the thickness of the bottom electrode, one need only add additional support layers rather than increase the thickness of an existing top support layer. With the only variable then being the thickness of the bottom electrode and the motivation of achieving increased capacitance in a semiconductor device via increasing aspect ratio of the bottom electrode, as shown by Yoon, a person of ordinary skill in the art would have the motivation and the teachings to achieve said motivation by optimizing the thickness range ratio as taught by Yoon.
Therefore, a prima facie case of obviousness exists prior to the effective filing date of the instant application to modify the semiconductor device of Zhao with the thickness ratio taught by Yoon for the benefit of improved capacitance (Yoon, Col 7, lines 57-61) and optimize the taught thickness ratio of Yoon from 1.0%-14.0% to 3.0%-8.0% via routine experimentation of a recognized result-effective variable (i.e., the thickness of the bottom electrode).
Regarding claim 2, Zhao in view of Yoon discloses the semiconductor device according to claim 1.
Zhao further discloses wherein the bottom electrode (lower electrode layer 33) comprises: a bottom portion positioned over the substrate and extending parallel to a top surface of the substrate; a first wall portion extending upward and from the bottom portion; and a second wall portion extending upward and from the bottom portion, and distant from the first wall portion (Zhao FIGs. 1, 3; paragraph [0058]; see below annotated Zhao FIG. 1).
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Regarding claim 3, Zhao in view of Yoon discloses the semiconductor device of claim 2.
Zhao further discloses wherein the top support layer (the second insulating layer 324) is attached on the second wall portion (Zhao FIGs. 1, 15; paragraph [0056-0057]; see above annotated Zhao FIG. 1).
Regarding claim 4, Zhao in view of Yoon discloses the semiconductor device of claim 3.
Zhao further discloses wherein a top surface of the first wall portion is lower than a top surface of the second wall portion (Zhao FIGs. 1, 15; see above annotated Zhao FIG. 1).
Regarding claim 5, Zhao in view of Yoon discloses the semiconductor device of claim 4.
Zhao further discloses wherein a dimension between the first wall portion and the second wall portion are tapered towards the bottom portion (Zhao FIGs. 1, 16, element 33, see also above annotated Zhao FIG. 1).
Regarding claim 6, Zhao in view of Yoon discloses the semiconductor device of claim 1.
Zhao further discloses further comprising a bottom support layer (insulating layer 31) positioned below and distant from the top support layer (second insulating dielectric layer 324), wherein the bottom support layer laterally surrounds the bottom electrode (Zhao FIG. 1, element 31).
Regarding claim 7, Zhao in view of Yoon discloses the semiconductor device of claim 6.
Zhao further discloses further comprising a middle support layer (first insulating dielectric layer 322) positioned between the bottom support layer (insulating layer 31) and the top support layer (second insulating dielectric layer 324), wherein the second support layer (interpreted as stated above as the middle support layer) is distant from both the bottom support layer and the top support layer, and laterally surrounds the bottom electrode (Zhao FIGs. 1, 16; paragraphs [0056-0057]).
Regarding claim 8, Zhao in view of Yoon discloses the semiconductor device of claim 7.
Zhao further discloses further comprising a dielectric layer (capacitor dielectric layer 34) conformally covering the bottom electrode, the bottom support layer, the middle support layer, and the top support layer (Zhao FIG. 1 and paragraph [0059]).
Regarding claim 9, Zhao in view of Yoon discloses the semiconductor device of claim 8.
Zhao further discloses further comprising a top electrode (upper electrode layer 35) conformally covering the dielectric layer (capacitor dielectric layer 34; see Zhao FIG. 1 and paragraph [0060]).
Regarding claim 10, Zhao in view of Yoon discloses the semiconductor device of claim 9.
Zhao further discloses further comprising a grounding layer (semiconductor layer 5) positioned on the top electrode (upper electrode layer 35; see Zhao FIG. 1 and paragraphs [0067-0068]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lai et al. (US PGPub 2022/0020752 A1 Lai et al.) discloses a capacitor with similar structure of multiple supporting layers.
You et al. (US PGPub 2023/0171947 A1) discloses a semiconductor device with a similar capacitor structure of high aspect-ratio, multiple supporting layers, and conformal electrode-dielectric-electrode layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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