DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al (US Pub No. 20100230779), in view of Yeh et al (US Patent No. 6943098).
With respect to claim 1, Anderson et al discloses providing a silicon-on-insulator substrate (14,16,12, Fig.2) including a semiconductor film (14), a carrier substrate (12) and a buried insulating layer (16) located between the carrier substrate and the semiconductor film (Fig.2); forming a trench extending through the semiconductor film and the buried insulating layer and into the carrier substrate (22,Fig.1); depositing a layer of polycrystalline semiconductor material (46, Para 28) to cover a dielectric layer (42) and further fill said trench to provide a trap-rich region in the silicon-on-insulator substrate (because the structure as described in the claim it is the same, Fig.3) that is not covered by the semiconductor film and the buried insulating layer (where trench is formed is not covered by the SOI). Anderson et al discloses that layer 42 is dielectric liner which is any suitable dielectric material or combination of dielectric material such as SioO2 (Para 28), however, it does not explicitly disclose performing an ion implantation of a non-doping species at side walls and a bottom of the trench to form an interface layer. On the other hand, Yeh et al discloses by ion implanting oxygen or argon the liner silicon oxide growth is improved (Lines 41-45, Col5, claim 7). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Anderson et al according to the teachings of the Yeh et al such that argon is implanted at side walls and a bottom of the trench to form an interface layer, thereby improving the growth of silicon oxide liner; this would improve process efficiency.
With respect to claim 2, Anderson et al discloses further comprising planarizing said layer of polycrystalline semiconductor material so that an upper surface of the polycrystalline semiconductor material filling said trench is coplanar with an upper surface of the semiconductor film (Fig.3, Para 28).
With respect to claim 3, the arts cited above do not explicitly disclose wherein the silicon-on-insulator substrate is a fully depleted silicon-on-insulator substrate, the semiconductor film including a fully depleted semiconductor material. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that semiconductor layer is thin enough in order to have a silicon-on-insulator substrate is a fully depleted silicon-on-insulator substrate, thereby the cutting cost and improving performance.
With respect to claim 4, the term wherein the carrier substrate is a high-resistivity substrate (high resistivity substrate is a relative term applicant need to specify the material to distinguish what is high resistivity substrate). Furthermore, it would have been obvious to one ordinary skill in the art to modify arts cited above such that high-resistivity substrate is used for RF or telecommunication applications.
With respect to claim 5, Yeh et al discloses, wherein the non-doping species is selected from the group consisting of: argon and germanium (claim 8).
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al (US Pub No. 20100230779).
With respect to claim 6, Anderson et al discloses: providing a silicon-on-insulator substrate (14,16,12, Fig.3) including a semiconductor film (14), a carrier substrate (12) and a buried insulating layer (16) located between the carrier substrate and the semiconductor film (Fig.3); forming a trench extending through the semiconductor film and the buried insulating layer and into the carrier substrate (Fig.1); forming a silicon oxide liner (42, Para 28); depositing a layer of polycrystalline semiconductor material to cover the silicon oxide liner (Para 28) and further fill said trench with polycrystalline semiconductor material (Fig.3) to provide a trap-rich region in the silicon-on-insulator substrate (Fig.3) that is not covered by the semiconductor film and the buried insulating layer (Fig.3). However, Anderson et al does not explicitly disclose oxidizing the sidewall and bottom of the trench to form an oxidized interface layer. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Anderson et al such that oxidizing the sidewall and bottom of the trench to form an oxidized interface layer, in order to form a silicon oxide liner economically.
With respect to claim 7, Anderson et al discloses further comprising planarizing said layer of polycrystalline semiconductor material so that an upper surface of the polycrystalline semiconductor material filling said trench is coplanar with an upper surface of the semiconductor film (Fig.3, Para 28).
With respect to claim 8, the arts cited above do not explicitly disclose wherein the silicon-on-insulator substrate is a fully depleted silicon-on-insulator substrate, the semiconductor film including a fully depleted semiconductor material. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the Anderson et al such that semiconductor layer is thin enough in order to have a silicon-on-insulator substrate is a fully depleted silicon-on-insulator substrate, thereby the cutting cost and improving performance.
With respect to claim 9, the term wherein the carrier substrate is a high-resistivity substrate (high resistivity substrate is a relative term applicant need to specify the material to distinguish what is high resistivity substrate). Furthermore, It would have been obvious to one ordinary skill in the art to modify Anderson et al such that high-resistivity substrate is used for RF or telecommunication applications.
With respect to claim 10, as was described in claim 6, wherein oxidizing comprises performing one of a thermal oxidization (please refer to claim 6). Anderson et al does not explicitly disclose the limitations of the claim 10. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Anderson et al such that thermal oxidation is used to form silicon oxide liner, because it is very inexpensive process which does not require additional equipment.
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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