DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars” as found in claim 1, and the first and second bit line sense amplifiers as found in claim 6, must be shown or the feature(s) canceled from the claim(s). Note the instant specification states “Memory cells (not illustrated) may be disposed at intersections between the word lines WL and the bit line pillars BLP, respectively” (¶19). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 1) It is unclear what is required by “a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines”. The limitation appears to being by defining word lines as being multilayered, but then M word lines are meant to be arranged in each layer. Each layer here would be a layer of the word line, and the word lines would then need to be arranged within themselves.
During examination, the quoted limitation above was read as “a plurality of word lines formed at N layers, wherein M word lines are arranged in each layer”.
Claims 2-8 inherit this rejection for indefiniteness.
Furthermore, the structure required by “a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively” is unclear, as this arrangement is not shown.
During examination, this quoted limitation was understood to require only that a plurality of memory cells is connected to one of the plurality of word lines and one of the plurality of bit lines.
Claims 2-8 inherit this rejection for indefiniteness.
Rejection 1/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (US 2009/0290402).
(Re Claim 9) Song teaches a memory comprising: a plurality of word lines (WL11+WL12; Fig. 7); a plurality of bit lines (BL11+BL12+BL21+BL22; Fig. 9); and a plurality of memory cells (MC11+MC12) connected to one of the plurality of word lines and one of the plurality of bit lines, wherein two or more word lines of the plurality of word lines are grouped and driven together (WL11+WL12 are grouped together at WL1; Fig. 7).
(Re Claim 10) Song teaches the memory of claim 9, wherein the grouped word lines include a first word line (WL12) and a second word line (WL11), and among the plurality of bit lines, first bit lines (BL11+BL21) connected to memory cells connected to the first word line and second bit lines (BL12+BL22) connected to memory cells connected to the second word line do not overlap each other (Fig. 7).
Rejection 2/2
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0257366), Lung (US 2024/0147877), and Lan et al. (US 2013/0170283).
(Re Claim 1) Lee teaches a memory comprising: a plurality of word lines (WL1+WL2; Fig. 7) formed of N layers (3; Fig. 7), M word lines (2; Fig. 7) being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more (Fig. 7); a plurality of bit line pillars (BL; Fig. 7); and a plurality of memory cells (MC1+MC2) disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively.
Lee has not been shown to explicitly teach a memory wherein two or more word lines of the plurality of word lines are grouped and driven together.
Lung teaches laterally stacking memory devices that are identical to each other to form an array of memory cells for memory (“respective instances of Group of Unit Cells 104 of FIG. 1D) is enabled to operate either independently of others of the groups or in conjunction with others of the groups, as controllable by circuitry additional to Array of 3D Cross Point Memory Cells 105”; Fig. 1E, ¶34).
A PHOSITA would find it obvious to form additional lateral copies of the memory described by Lee (300; Fig. 7) to increase the amount of information stored by the memory. See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Lan teaches forming a plurality of word lines (840a-h+842a-h; Fig. 14) in a layer (top view of one layer; ¶142) such that two or more word lines of the plurality of word lines are grouped and driven together (“[b]iasing a word line comb will bias all 16 (or other number of) word line fingers that are part of that word line comb”; ¶143).
A PHOSITA would find it obvious to physically connect the plurality of word lines of modified Lee in the alternating way taught by Lan, in each layer, as “using one or more word line drivers to drive multiple word lines reduces the number of wires needed from the word line drivers to the word lines, thereby saving room, simplifying routing, reducing power and reducing the chance of a fault” (Lan: ¶139).
Lan further teaches using 16 word lines with as many associated memory cells (¶139).
A PHOSITA would find it obvious to form 8 copies of the memory (300; Fig. 7) taught by Lee, as this is a known number of word lines that may be used in a memory device that may be driven using the comb pattern of Lan, allowing for predictable driving behavior when accessing the bits stored within the memory. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Modified Lee then teaches the memory comprising:
a plurality of word lines (left and right word lines numbered 1-8; See modified Lee markups below) formed of N layers (3; Fig. 7), M word lines being arranged in each layer (16 word lines per layer), among the plurality of word lines, where each of N and M is an integer of 2 or more;
a plurality of bit line pillars (each BL copy from Lee’s Fig. 7 now shown in the modified Lee markup that is a leftmost or center bit line pillar); and
a plurality of memory cells (each respective MC; Lee’s Fig. 7) disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively,
wherein two or more word lines (the left word lines labelled 1 and 2; modified Lee markups) of the plurality of word lines are grouped and driven together (Lan: ¶139).
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(Re Claim 2) Modified Lee teaches the memory of claim 1, wherein, among the plurality of word lines, the grouped word lines word lines are included in a same layer (the top layer of the 3 layers shown in Lee’s Fig. 7).
(Re Claim 5) Modified Lee teaches the memory of claim 1, wherein each of the plurality of memory cells includes a transistor (each respective TR, e.g., TR1, associated with each MC; ¶¶62, 90) and a capacitor (each respective CAP, e.g., CAP1, associated with each MC; ¶¶62, 90).
(Re Claim 7) Modified Lee teaches the memory of claim 1, wherein the grouped word lines among the plurality of word lines are shorted to each other (Lan: ¶139).
(Re Claim 8) Modified Lee teaches the memory of claim 1, wherein each of the plurality of bit line pillars is disposed to pass between two word lines in each of the N layers (Lee: Fig. 7).
(Re Claim 9) Lee teaches a memory comprising: a plurality of word lines (WL1+WL2; Fig. 7); a plurality of bit lines (BL; Fig. 7); and a plurality of memory cells (MC1+MC2) connected to one of the plurality of word lines and one of the plurality of bit lines (Fig. 7).
Lee has not been shown to teach a memory wherein two or more word lines of the plurality of word lines are grouped and driven together.
Lung teaches laterally stacking memory devices that are identical to each other to form an array of memory cells for memory (“respective instances of Group of Unit Cells 104 of FIG. 1D) is enabled to operate either independently of others of the groups or in conjunction with others of the groups, as controllable by circuitry additional to Array of 3D Cross Point Memory Cells 105”; Fig. 1E, ¶34).
A PHOSITA would find it obvious to form additional lateral copies of the memory described by Lee (300; Fig. 7) to increase the amount of information stored by the memory. See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Lan teaches forming a plurality of word lines (840a-h+842a-h; Fig. 14) in a layer (top view of one layer; ¶142) such that two or more word lines of the plurality of word lines are grouped and driven together (“[b]iasing a word line comb will bias all 16 (or other number of) word line fingers that are part of that word line comb”; ¶143).
A PHOSITA would find it obvious to physically connect the plurality of word lines of modified Lee in the alternating way taught by Lan, in each layer, as “using one or more word line drivers to drive multiple word lines reduces the number of wires needed from the word line drivers to the word lines, thereby saving room, simplifying routing, reducing power and reducing the chance of a fault” (Lan: ¶139).
Lan further teaches using 16 word lines with as many associated memory cells (¶139).
A PHOSITA would find it obvious to form 8 copies of the memory (300; Fig. 7) taught by Lee, as this is a known number of word lines that may be used in a memory device that may be driven using the comb pattern of Lan, allowing for predictable driving behavior when accessing the bits stored within the memory. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Modified Lee then teaches the memory comprising:
a plurality of word lines (left and right word lines numbered 1-8; See modified Lee markups below) formed of N layers (3; Fig. 7);
a plurality of bit lines (each BL copy from Lee’s Fig. 7 now shown in the modified Lee markup); and
a plurality of memory cells (each respective MC; Lee’s Fig. 7) connected to one of the plurality of word lines and one of the plurality of bit lines (each memory cell is respectively connected to a word line and bit line as detailed in Lee’s Fig. 7),
wherein two or more word lines (the left word lines labelled 1 and 2; modified Lee markups) of the plurality of word lines are grouped and driven together (Lan: ¶139).
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(Re Claim 10) Modified Lee teaches the memory of claim 9, wherein the grouped word lines include a first word line (left word line labelled 1; modified Lee’s markup) and a second word line (left word line labelled 2; modified Lee’s markup), and among the plurality of bit lines, first bit lines (bit lines between left and right word line 1; modified Lee’s markup) connected to memory cells (each memory cells as would be seen in Lee’s Fig. 7) connected to the first word line and second bit lines (bit lines between left and right word line 2; modified Lee’s markup) connected to memory cells (each memory cells as would be seen in Lee’s Fig. 7) connected to the second word line do not overlap each other (modified Lee’s markups).
(Re Claim 11) Modified Lee teaches the memory of claim 9, wherein each of the plurality of memory cells includes a transistor (each respective TR, e.g., TR1, associated with each MC; ¶¶62, 90) and a capacitor (each respective CAP, e.g., CAP1, associated with each MC; ¶¶62, 90).
Claims 3-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0257366), Lung (US 2024/0147877), and Lan et al. (US 2013/0170283) as respectively applied to claims 1 and 2 above, and further in view of You et al. (US 2016/0254064).
(Re Claim 3) Modified Lee teaches the memory of claim 2, but has not been explicitly shown to teach the memory wherein the plurality of bit line pillars are mutually electrically connected while forming a group in units of L, where L is an integer of 2 or more.
You teaches connecting a plurality of bit lines (BLx and BLBx; Fig. 3) across different word lines (WLx; Fig. 3) to sense amplifiers (330+340; Fig. 3).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to connected the bit line pillars across word lines in the manner taught by You in order to allow for sense amplifiers to sense and amplify the data associated with a particular column (¶40).
This results in modified Lee teaches the memory wherein the plurality of bit line pillars are mutually electrically connected (You: ¶40) while forming a group (the eight leftmost bit lines as seen in modified Lee’s markup) in units of L, where L is an integer of 2 or more (8 as seen in modified Lee’s markup). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
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(Re Claim 4) Modified Lee teaches the memory of claim 3, wherein, among the bit line pillars, bit line pillars intersecting the grouped word lines are not mutually electrically connected (the leftmost and the center bit line pillar between the grouped left word lines 1 and 2 are not mutually electrically connected).
(Re Claim 6) Modified Lee teaches the memory of claim 1, but has not been shown to teach the memory wherein a first-half of the plurality of bit line pillars are connected to first bit line sense amplifiers disposed on a first side in a direction perpendicular to the plurality of bit line pillars, and a second-half of the plurality of bit line pillars are connected to second bit line sense amplifiers disposed on a second side in the direction perpendicular to the plurality of bit line pillars.
You teaches connecting a plurality of bit lines (BLx and BLBx; Fig. 3) across different word lines (WLx; Fig. 3) to first and second bit line sense amplifiers (respectively the plurality of sense amplifiers respectively associated with 330 and 340; Fig. 3, ¶40), wherein the first bit line sense amplifiers are disposed on a first side (a top side; Fig. 3) and the second bit line sense amplifiers are disposed on a second side (a bottom side; Fig. 3), wherein the first and second bit line sense amplifiers are connected to alternating bit lines (Fig. 3).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to connected the bit line pillars across word lines using bit lines in the manner taught by You in order to allow for sense amplifiers to sense and amplify the data associated with a particular column (¶40).
This results in modified Lee teaches the memory wherein the a first-half of the plurality of bit line pillars (leftmost bit line pillars; modified Lee’s markups) are connected to first bit line sense amplifiers disposed on a first side (the “top” side as seen in the modified Lee markups) in a direction perpendicular to the plurality of bit line pillars (modified Lee markup), and a second half of the plurality of bit line pillars (center bit line pillars; modified Lee’s markup) are connected to second bit line sense amplifiers disposed on a second side (the “bottom” side as seen in the modified Lee markups) in the direction perpendicular to the plurality of bit line pillars (modified Lee markups).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights