DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars” as found in claim 1, and the first and second bit line sense amplifiers as found in claim 6, must be shown or the feature(s) canceled from the claim(s). Note the instant specification states “Memory cells (not illustrated) may be disposed at intersections between the word lines WL and the bit line pillars BLP, respectively” (¶19). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112(b) rejections are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0257366), Lung (US 2024/0147877), and Lan et al. (US 2013/0170283), all of record.
(Re Claim 1) Lee teaches a memory comprising: a plurality of word lines (WL1+WL2; Fig. 7) formed of N layers (3; Fig. 7), M word lines (2; Fig. 7) being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more (Fig. 7); a plurality of bit line pillars (BL; Fig. 7); and a plurality of memory cells (MC1+MC2) disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively.
Lee has not been shown to explicitly teach a memory wherein two or more word lines of the plurality of word lines are grouped and shorted to each other to be driven together, and
wherein the plurality of bit line pillars and a plurality of bit lines connected thereto are arranged such that first date read from first memory cell connected to a first word line of the shorted word lines and second data read from second memory cells connected to a second word line of the shorted word lines are routed to distinct, non-overlapping bit lines among the plurality of bit lines to prevent data collisions during simultaneous driving of the shorted word lines.
Lung teaches laterally stacking memory devices that are identical to each other to form an array of memory cells for memory (“respective instances of Group of Unit Cells 104 of FIG. 1D) is enabled to operate either independently of others of the groups or in conjunction with others of the groups, as controllable by circuitry additional to Array of 3D Cross Point Memory Cells 105”; Fig. 1E, ¶34).
A PHOSITA would find it obvious to form additional lateral copies of the memory described by Lee (300; Fig. 7) to increase the amount of information stored by the memory. See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Lan teaches forming a plurality of word lines (840a-h+842a-h; Fig. 14) in a layer (top view of one layer; ¶142) such that two or more word lines of the plurality of word lines are grouped and driven together (“[b]iasing a word line comb will bias all 16 (or other number of) word line fingers that are part of that word line comb”; ¶143).
A PHOSITA would find it obvious to physically connect the plurality of word lines of modified Lee in the alternating way through the use of connections that are perpendicular to the word lines as taught by Lan, in each layer, as “using one or more word line drivers to drive multiple word lines reduces the number of wires needed from the word line drivers to the word lines, thereby saving room, simplifying routing, reducing power and reducing the chance of a fault” (Lan: ¶139).
Lan further teaches using 16 word lines with as many associated memory cells (¶139).
A PHOSITA would find it obvious to form 8 copies of the memory (300; Fig. 7) taught by Lee, as this is a known number of word lines that may be used in a memory device that may be driven using the comb pattern of Lan, allowing for predictable driving behavior when accessing the bits stored within the memory. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Modified Lee then teaches the memory comprising:
a plurality of word lines (left and right word lines numbered 1-8; See modified Lee markups below) formed of N layers (3; Fig. 7), M word lines being arranged in each layer (16 word lines per layer), among the plurality of word lines, where each of N and M is an integer of 2 or more;
a plurality of bit line pillars (each BL copy from Lee’s Fig. 7 now shown in the modified Lee markup that is a leftmost or center bit line pillar); and
a plurality of memory cells (each respective MC; Lee’s Fig. 7) disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively,
wherein two or more word lines (the left word lines labelled 1 and 2; modified Lee markups) of the plurality of word lines are grouped and shorted to each other to be driven together (from Lan, the word lines are alternately shorted to each other in modified Lee through a connection corresponding to Lan’s 840 or 842 ¶139; see the diagrams showing modified Lee below).
Lan also teaches forming at least four memory cells (Fig. 14 shows at least four bit line pillars 852, and each bit line pillar has two memory cells connected on opposite sides; see also Fig. 11 and ¶44).
A PHOSITA would find it obvious to form at least four copies of the memory cells MCA300 as described by Lee (Fig. 7, ¶67), in the manner taught by Lan, to increase the amount of information stored by the memory. See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Furthermore, Lan teaches forming bit lines (each GBL; Fig. 1 and 7; ¶42) underneath memory cells (Fig. 1 and 6, ¶133); underneath and perpendicular to word lines (each WL; Fig. 1 and 7); and connected to bit line pillars (each corresponding LBL; ¶115).
A PHOSITA would find it obvious to form bit lines connected to each bit line pillar and perpendicular to the word lines of modified Lee, such that the bit lines are beneath these elements, using the corresponding connections taught by Lan, as this arrangement allows for exterior access to the bit lines underneath each bit line pillar without cutting through the word lines, which would increase the routing length.
This results in the plurality of bit line pillars and a plurality of bit lines (from Lan) connected thereto (modified Lee markups below) are arranged such that first date read from first memory cells (the two memory cells left of center as seen in the modified Lee markups below) connected to a first word line (left word line 1) of the shorted word lines and second data read from second memory cells (the two memory cells right of center as seen in the modified Lee markups below) connected to a second word line (left word line 2) of the shorted word lines are routed to distinct, non-overlapping bit lines (the two bit lines on the left versus the two bit lines on the right) among the plurality of bit lines to prevent data collisions during simultaneous driving of the shorted word lines.
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(Re Claim 2) Modified Lee teaches the memory of claim 1, wherein, among the plurality of word lines, the grouped word lines word lines are included in a same layer (the top layer of the 3 layers shown in Lee’s Fig. 7).
(Re Claim 3) Modified Lee teaches the memory of claim 2, but has not been explicitly shown to teach the memory wherein the plurality of bit line pillars are mutually electrically connected while forming a group in units of L, where L is an integer of 2 or more (groups in units of 8 as seen in modified Lee’s markup due to Lan’s bit line connections).
(Re Claim 5) Modified Lee teaches the memory of claim 1, wherein each of the plurality of memory cells includes a transistor (each respective TR, e.g., TR1, associated with each MC; ¶¶62, 90) and a capacitor (each respective CAP, e.g., CAP1, associated with each MC; ¶¶62, 90).
(Re Claim 8) Modified Lee teaches the memory of claim 1, wherein each of the plurality of bit line pillars is disposed to pass between two word lines in each of the N layers (Lee: Fig. 7).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0257366), Lung (US 2024/0147877), and Lan et al. (US 2013/0170283) as respectively applied to claims 1 and 3 above, and further in view of You et al. (US 2016/0254064), all of record.
(Re Claim 4) Modified Lee teaches the memory of claim 3, but has not been shown explicitly to teach memory wherein, among the bit line pillars, bit line pillars intersecting the grouped word lines are not mutually electrically connected.
You teaches connecting a plurality of bit lines (BLx and BLBx; Fig. 3) across different word lines (WLx; Fig. 3) to sense amplifiers (330+340; Fig. 3).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to connected the bit line pillars across word lines in the manner taught by You in order to allow for sense amplifiers to sense and amplify the data associated with a particular column (¶40). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
This results in modified Lee teaches the memory wherein the plurality of bit line pillars are mutually electrically connected (You: ¶40) while forming a group (the eight leftmost bit lines as seen in modified Lee’s markup) in units of L, where L is an integer of 2 or more (8 as seen in modified Lee’s markup), and among the bit line pillars, bit line pillars intersecting the grouped word lines are not mutually electrically connected (the leftmost and the center bit line pillar between the grouped left word lines 1 and 2 are not mutually electrically connected; see the markup for modified Lee below).
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(Re Claim 6) Modified Lee teaches the memory of claim 1, but has not been shown to teach the memory wherein a first-half of the plurality of bit line pillars are connected to first bit line sense amplifiers disposed on a first side in a direction perpendicular to the plurality of bit line pillars, and a second-half of the plurality of bit line pillars are connected to second bit line sense amplifiers disposed on a second side in the direction perpendicular to the plurality of bit line pillars.
You teaches connecting a plurality of bit lines (BLx and BLBx; Fig. 3) across different word lines (WLx; Fig. 3) to first and second bit line sense amplifiers (respectively the plurality of sense amplifiers respectively associated with 330 and 340; Fig. 3, ¶40), wherein the first bit line sense amplifiers are disposed on a first side (a top side; Fig. 3) and the second bit line sense amplifiers are disposed on a second side (a bottom side; Fig. 3), wherein the first and second bit line sense amplifiers are connected to alternating bit lines (Fig. 3).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to connected the bit line pillars across word lines using bit lines in the manner taught by You in order to allow for sense amplifiers to sense and amplify the data associated with a particular column (¶40).
This results in modified Lee teaches the memory wherein the a first-half of the plurality of bit line pillars (leftmost bit line pillars; modified Lee’s markups) are connected to first bit line sense amplifiers disposed on a first side (the “top” side as seen in the modified Lee markups) in a direction perpendicular to the plurality of bit line pillars (modified Lee markup), and a second half of the plurality of bit line pillars (center bit line pillars; modified Lee’s markup) are connected to second bit line sense amplifiers disposed on a second side (the “bottom” side as seen in the modified Lee markups) in the direction perpendicular to the plurality of bit line pillars (modified Lee markups).
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Response to Arguments
Applicant's arguments filed 8/3/2026 have been fully considered but they are not persuasive.
Drawings
Though Applicant points to Fig. 5 and 9 to show memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars (remarks, p. 5), Fig. 5 and 9 are circuit diagrams, which do not ordinarily convey information related to how far features are away from each other, and so it cannot be said that memory cells are disposed at intersections between the plurality of word lines and the plurality of bit line pillars.
Furthermore, though Applicant points to Fig. 3 and 7 to show bit line sense amplifiers (remarks, p. 5), but these figures depict bit line sense amplifier arrays, which are described as elements that “may include a plurality of bit line sense amplifiers” (instant: ¶¶26, 43). And so the bit line sense amplifiers are evidently not shown.
Therefore, the drawing objections are maintained.
Claim Rejections Under 35 U.S.C. §103
Applicant argues that the proposed combination of Lee and Lan is inoperable due to simultaneous activation of memory cells that share the same bit line pillar (remarks, p. 9). However, Lan shows that individual memory elements may be selected (“An individual memory element Mzxy is therefore addressable by placing proper voltages on the local bit line LBLxy and word line WLzy between which the memory element is connected” (¶44); see also ¶¶42-43). It is unclear why such a configuration would simultaneously activate memory cells that share the same bit line pillar and cause data collisions.
Compare Lan’s Fig. 11 to the instant Fig. 8.
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As for the benefits that Applicant argues (remarks, p. 9), both the Applicant and Lan teach shorting word lines to reduce driver area (Lan: “Thus, the word line drivers have been too big to fit underneath the memory array. One proposed solution is to connect one word line driver to a group of multiple word lines connected together, where a memory system will have many of such groups…In one example, the 16 word lines are connected together to form a comb shape. However, other shapes can also be used. Using one word line driver to drive 16 (or a different number of) word lines in a single comb (or other shaped structure) reduces the number of word line drivers need.” (¶139)).
The remainder of Applicant’s arguments are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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