DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Preliminary Amendment
Claims 21-27 have been cancelled; and claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statements filed on 04/03/2024, 11/27/2024, and 1/09/2026 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 13, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saleh et al. (US 2021/0097013 A1, hereinafter “Saleh”) in view of Song et al. (US 2015/0130024 A1, hereinafter “Song”).
In regards to claim 1, Saleh discloses (See, for example, Fig. 3) a semiconductor device comprising:
an interconnect package comprising at least one dielectric layer (308) and at least one first wiring trace (See, for example, 304) formed in the at least one dielectric layer (308), and
configured to connect a plurality of semiconductor chips (106-1, 106-2…) through the at least one first wiring trace (304).
Saleh fails to explicitly teach
wherein the interconnect package further comprises a capacitor on the at least one first wiring trace, the capacitor being coupled to the at least one first wiring trace.
Song while disclosing embedded passive devices teaches (See, for example, Figs. 2 and 3A-3B)
wherein the interconnect package further comprises a capacitor (205) on the at least one first wiring trace (105), the capacitor (205) being coupled to the at least one first wiring trace
(105).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to modify Saleh by Song because this would help provide a
local low-inductance charge reservoir proximate the bridged chips (chiplets) to reduce the
parasitic inductance and impedance in the power delivery path to those chips.
In regards to claim 13, Saleh discloses (See, for example, Fig. 3) an electronic device comprising:
a die stack comprising at least two semiconductor chips (106-1, 106-2, …);
an interconnect package (118, 304, 308) disposed below the die stack in a first direction (Perpendicular to carrier wafer 302) and connecting the semiconductor chips (106-1, 106-2, …); and
wherein the interconnect package (118, 304) has a smaller width than the die stack (106-1, 106-2, …) in a second direction (parallel to the carrier wafer) which intersects the first
direction (the rectangular active bridge chiplet 118 spanning only across the boundary/middle region of the GPU chiplets and being narrower than the chiplet die stack it couples; See Fig. 3).
Saleh is silent about a capacitor disposed inside the interconnect package and connected to at least one of the semiconductor chips, and configured to be connected to a voltage source.
Song discloses (See, for example, Figs. 2 and 3A-3B) a capacitor (205) disposed inside the interconnect package and connected to at least one of the semiconductor chips (100), and configured to be connected to a voltage source (power supply voltage (VDD), 335).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to modify Saleh by Song because this would help provide a local low-inductance charge reservoir proximate the bridged chips (chiplets) to reduce the parasitic inductance and impedance in the power delivery path to those chips.
In regards to claim 17, Saleh discloses (See, for example, Fig. 3) an electronic system comprising:
a substrate (302) comprising a plurality of connection terminals (310/312) on at least one of a first surface and a second surface thereof, the second surface being opposite to the first surface; and
at least one semiconductor package comprising a plurality of semiconductor chips (106-1, 106-2, …), and at least one interconnect package (118, 304, 308),
wherein at least one of the semiconductor chips (106-1, 106-2, …) is connected to at least one of the connection terminals (310/312) of the substrate,
wherein the at least one interconnect package comprises: at least one dielectric layer (308); and
at least one first wiring trace (304) included in the at least one dielectric layer (308), and
connecting the semiconductor chips (106-1, 106-2, …).
Saleh is silent about at least one capacitor coupled to the at least one first wiring trace.
Song discloses (See, for example, Figs. 2 and 3A-3B) at least one capacitor (205) coupled to the at least one first wiring trace (105).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to modify Saleh by Song because this would help provide a local low-inductance charge reservoir proximate the bridged chips (chiplets) to reduce the parasitic inductance and impedance in the power delivery path to those chips.
In regards to claim 2, Saleh as modified above discloses (See, for example, Fig. 3) that wherein
the semiconductor chips (106-1, 106-2, …) are disposed above the interconnect package (118,
304, 308) in a first direction (perpendicular to the carrier wafer 302).
In regards to claim 20, Saleh as modified above discloses (See, for example, Figs. 2 and 3A-3B, Song) wherein the at least one capacitor (205) is configured to be connected to a voltage source (power supply voltage (VDD), 335).
Claims 3-9, 14-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Saleh in view of Song and Kung et al. (US 2023/0215816 A1, hereinafter “Kung”).
In regards to claims 3-9, Saleh as modified above discloses all limitations of claim 1 except that
further comprising a redistribution substrate in which the interconnect package is included, and
wherein the redistribution substrate has a greater lateral width than the interconnect package in a second direction that intersects a first direction (claim 3); further comprising a redistribution substrate in which the interconnect package is included, wherein the semiconductor chips are disposed above the redistribution substrate in a first direction, wherein the redistribution substrate comprises at least one redistribution layer in which at least one second wiring trace is formed, and wherein the at least one second wiring trace connects the at least one first wiring trace to the semiconductor chips (claim 4); further comprising a package substrate disposed below the redistribution substrate, wherein the package substrate comprises a plurality of connection structures therein and a plurality of connection terminals on a first surface and a second surfaces thereof, the second surface being opposite to the first surface, wherein the connection structures are connected to the connection terminals, respectively, and wherein at least one of the connection terminals is connected to the at least one first wiring trace through the at least one second wiring trace (claim 5); and further comprising at least one additional capacitor on a first surface or a second surface of the package substrate opposite to the first surface, wherein the at least one additional capacitor has a greater size than the capacitor in the interconnect package (claim 6); wherein the semiconductor chips are disposed above the interconnect package in a first direction, wherein the capacitor is disposed in an upper portion of the interconnect package which is closer to the semiconductor chips than a lower portion of the interconnect package (claim 7); wherein the at least one dielectric layer comprises a plurality of dielectric layers, and wherein a thickness of the capacitor is smaller than that of one of the dielectric layers in a first direction (claim 8); wherein the at least one first wiring trace comprises: a power wiring trace on which the capacitor is disposed, the power wiring trace being configured to connect at least one of the semiconductor chips to a voltage source; and a signal wiring trace configured to connect the semiconductor chips (claim 9).
Kung while disclosing a package structure teaches (See, for example, Fig. 2) further comprising a redistribution substrate (3, 6) in which the interconnect package (includes 2) is included, and wherein the redistribution substrate (3, 6) has a greater lateral width than the interconnect package (2) in a second direction (parallel to the RDLs (3, 6) main surfaces) that intersects a first direction (perpendicular to the RDLs (3, 6) main surfaces);
further comprising a redistribution substrate (3, 6) in which the interconnect package (2) is included, wherein the semiconductor chips (4, 5) are disposed above the
redistribution substrate (3, 6) in a first direction (perpendicular to the RDLs main surface),
wherein the redistribution substrate (3, 6) comprises at least one redistribution layer in which at
least one second wiring trace (33/33) is formed, and wherein the at least one second wiring trace (31/33) connects the at least one first wiring trace (wiring layer over 32) to the semiconductor
chips (4, 5);
further comprising a package substrate (2) disposed below the redistribution
substrate (3), wherein the package substrate (2) comprises a plurality of connection structures
(See, for example, 254, 252) therein and a plurality of connection terminals (254, 252) on a first
surface and a second surfaces thereof, the second surface being opposite to the first surface,
wherein the connection structures are connected to the connection terminals (2545, 252),
respectively, and wherein at least one of the connection terminals (254, 252) is connected to the
at least one first wiring trace (wiring layer over 32) through the at least one second wiring trace
(32/33);
further comprising at least one additional capacitor (7) on a first surface or a second surface of
the package substrate opposite to the first surface, wherein the at least one additional capacitor
(7) has a greater size than the capacitor (25) in the interconnect package (2);
wherein the semiconductor chips (4, 5) are disposed above the interconnect package (2) in a first
direction, wherein the capacitor (25) is disposed in an upper portion of the interconnect package
(2) which is closer to the semiconductor chips (4, 5) than a lower portion of the interconnect
package (2);
wherein the at least one dielectric layer comprises a plurality of dielectric layers (14, 23, 28), and wherein a thickness of the capacitor (25) is smaller than that of one of the dielectric layers (14, 23, 28) in a first direction;
wherein the at least one first wiring trace comprises: a power wiring trace (power region 22, See also Par [0035]) on which the capacitor (25) is disposed, the power wiring trace (power region 22, See also Par [0035]) being configured to connect at least one of the semiconductor chips (4,
5) to a voltage source (see, Par [0047]); and a signal wiring trace (a bridge region 21, See, for
example, Par [0034]) configured to connect (See Par [0034]) the semiconductor chips (4, 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective
filing date of the invention to modify Saleh by Kung because this would help relieve the stress otherwise concentrated at the gap between the laterally adjacent semiconductor dice to prevent cracking of the redistribution layer corresponding to that gap.
In regards to claims 14 and 15, Saleh as modified above discloses all limitations of claim 13 except that
wherein the interconnect package comprises: a power wiring trace coupled to the capacitor; a signal wiring trace connecting the semiconductor chips (claim 14); the interconnect package is disposed below a boundary of the semiconductor chips in the first direction (claim 15).
Kung discloses (See, for example, Fig. 2) wherein the interconnect package comprises: a power wiring trace (power region 22, See also Par [0035]) coupled to the capacitor (25), a signal wiring
trace (a bridge region 21, See, for example, Par [0034]) connecting (See Par [0034]) the
semiconductor chips (4, 5); wherein the interconnect package (2) is disposed below a boundary of the semiconductor chips (4, 5) in the first direction.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective
filing date of the invention to modify Saleh by Kung because this would help relieve the stress otherwise concentrated at the gap between the laterally adjacent semiconductor dice to prevent cracking of the redistribution layer corresponding to that gap.
In regards to claim 19, Saleh as modified above discloses all limitations of claim 17 except that wherein the at least one first wiring trace comprises: a power wiring trace coupled to the at least
one capacitor; and a signal wiring trace connecting the semiconductor chips.
Kung discloses (See, for example, Fig. 2) wherein the at least one first wiring trace comprises: a power wiring trace (power region 22, See also Par [0035]) coupled to the at least one capacitor
(25); and a signal wiring trace (a bridge region 21, See, for example, Par [0034]) connecting (See Par [0034]) the semiconductor chips (4, 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective
filing date of the invention to modify Saleh by Kung because this would help relieve the stress otherwise concentrated at the gap between the laterally adjacent semiconductor dice to prevent cracking of the redistribution layer corresponding to that gap.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Saleh
in view of Song and Cheah et al. (US 2021/0193567 A1, hereinafter “Cheah”)
In regards to claim 10, Saleh as modified above discloses all limitations of claim 1 except that the semiconductor chips; a redistribution substrate below the semiconductor chips in a first direction, the redistribution substrate comprising the interconnect package therein; and a package substrate below the redistribution substrate in the first direction, the package substrate being connected to the redistribution substrate.
Cheah while disclosing an electronic device teaches (See, for example, Fig. 1A annotated and included below) the semiconductor chips (130, 132, 134); a redistribution substrate (RDL1, RDL2/116) below the semiconductor chips (130, 132, 134) in a first direction, the redistribution substrate (RDL1, RDL2/116) comprising the interconnect package (140) therein; and a package substrate (PS/114) below the redistribution substrate (RDL1, RDL2/116) in the first direction, the package substrate (PS/114) being connected to the redistribution substrate (RDL1, RDL2/116).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Saleh by Cheah because this would help improve the power integrity of the multi-chip package by reducing the AC loop inductance and power supply noise induced jitter (PSIJ) between the semiconductor dies and the power delivery network.
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In regards to claim 11, Saleh as modified above discloses (See, for example, Fig, 3) wherein the
interconnect package further comprises a support layer on which the at least one dielectric layer
is disposed, wherein the support layer comprises at least one of silicon, ceramic and glass, (See,
for example, “the active bridge chiplet 118 bridges multiple GPU chiplets 106 and therefore
is interchangeably referred to as …active silicon bridge.”, Pars [0022], [0023], and [0027]) and wherein at least one transistor is included in the support layer (“the active bridge chiplet
118 operates as a memory crossbar with a shared, unified last level cache (LLC) to provide inter-chiplet communications…”, See for example, Pars [0016], [0018], and [0022]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Saleh in view of Song and Cheah as applied to claim 11 above, and further in view of Dabral et al. (US 2024/0105699 A1, hereinafter “Dabral”).
In regards to claim 12, Saleh has modified above discloses all limitations of claim 11 except that wherein the interconnect package further comprises at least one through via formed in the support layer, and wherein the at least one through via connects the capacitor to the at least one transistor.
Dabral while disclosing 3D system and wafer constitution teaches (See, for example, Fig. 4A) wherein the interconnect package further comprises at least one through via (190) formed in the support layer (147), and wherein the at least one through via (190) connects the capacitor to the at least one transistor (“Devices 149 may be also formed within the silicon interconnect 122, including both passive (including trench capacitors) and active devices.”, See, for example, Par[0033]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Saleh by Dabral because this would help provide additional routing area enabling die partitioning and process node optimization, as well as flexibility for power delivery and integration of passive devices into the system.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Saleh in view of Song and Dabral.
In regards to claim 16, Saleh as modified above discloses all limitations of claim 13 except that wherein the interconnect package comprises: a dielectric layer in which the capacitor is disposed; and a support layer below the dielectric layer, the support layer comprising at least one transistor connected to the capacitor.
Dabral teaches (See, for example, Figs. 4A and 10) wherein the interconnect package comprises: a dielectric layer (116, See Fig. 10) in which the capacitor (113) is disposed; and a support layer (147) below the dielectric layer (116, See, Fig. 10), the support layer (147) comprising at least one transistor connected to the capacitor (“Devices 149 may be also formed within the silicon interconnect 122, including both passive (including trench capacitors) and active devices.”, See, for example, Par [0033]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Saleh by Dabral because this would help provide additional routing area enabling die partitioning and process node optimization, as well as flexibility for power delivery and integration of passive devices into the system.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Saleh in view of Song and LAI et al. (US 2024/0347407 A1, hereinafter “LAI”).
In regards to claim 18, Saleh as modified above discloses all limitations of claim 17 except that wherein the semiconductor chips comprise a system-on-chip (SoC) and a memory chip.
LAI while disclosing chip package structure teaches (See, for example, Fig. 1I, 4, 5, and 11) wherein the semiconductor chips (100S1, 100S2) comprise a system-on-chip (SoC) and a memory chip (See, for example, Pars [0023], [0039], [0060], and [0062]; and Claim 14).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Saleh by LAI because this would help improve the
reliability of the package by relieving the stress concentrated at the gap region between the adjacent dies through the differing modulus gap-filling layers.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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