CTNF 18/625,761 CTNF 101794 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-05 AIA Claim 6 recites the limitation " the third semiconductor regions " in line 4 of the claim. While it is acknowledged that there is antecedent basis for a single third semiconductor region, there is no explicit introduction of a plurality of third semiconductor regions, thus there is insufficient antecedent basis for this limitation in the claim. 07-34-05 AIA Claim 11 recites the limitation " the third semiconductor regions " in line 4 of the claim. While it is acknowledged that there is antecedent basis for a single third semiconductor region, there is no explicit introduction of a plurality of third semiconductor regions, thus there is insufficient antecedent basis for this limitation in the claim. 07-34-05 AIA Claim 19 recites the limitation " the third semiconductor regions " in line 5 of the claim. While it is acknowledged that there is antecedent basis for a single third semiconductor region, there is no explicit introduction of a plurality of third semiconductor regions, thus there is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 2, 7, 12, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Nishiguchi et al. (2022/0093788, hereafter Nishiguchi) . Regarding claim 1 , Nishiguchi discloses a semiconductor device comprising: a semiconductor layer (100, Fig. 1 par. 0021) including a first main surface (top) and a second main surface (bottom); a first electrode (20, Fig. 1, par. 0021) provided on the first main surface; a second electrode (10, Fig. 1, par. 0021) provided on the second main surface; a first semiconductor region (1, Fig. 1, par. 0021) of a first conductivity type, the first semiconductor region being provided in the semiconductor layer and located on the second electrode; a plurality of insulating regions (31, Fig. 1, par. 0024) provided in the semiconductor layer, configured to reach the first semiconductor region from the first main surface, and formed to extend in a second direction orthogonal to a first direction from the second electrode toward the first electrode; a plurality of third electrodes (30, Fig. 1, par. 0021) provided in the plurality of insulating regions and formed to extend in the second direction; a second semiconductor region (2, Fig. 1, par. 0021) of a second conductivity type provided, in the semiconductor layer, to be sandwiched between the plurality of insulating regions, to be located on the first semiconductor region, and to extend in the second direction; a third semiconductor region (3, Fig. 1, par. 0021) of the first conductivity type, the third semiconductor region being provided in the semiconductor layer and located between the second semiconductor region and the first electrode; and a carrier conduction part (4, Fig. 1, par. 0024) provided to extend in the second direction in the second semiconductor region and electrically connected to the first electrode via a connection part not penetrating the third semiconductor region. Regarding claim 2 , Nishiguchi discloses a semiconductor device wherein the carrier conduction part (4, Fig. 1) includes a semiconductor of the second conductivity type having an impurity concentration of the second conductivity type higher than an impurity concentration of the second conductivity type of the second semiconductor region (par. 0024). Regarding claim 7 , Nishiguchi discloses a semiconductor device wherein the carrier conduction part contains metal or polysilicon (4, par. 0035). Regarding claim 12 , Nishiguchi discloses a semiconductor device wherein the carrier conduction part (4, Figs. 1-2) is provided at a position equidistant from the adjacent third electrodes (30, Figs. 1-2). Regarding claim 20 , Nishiguchi discloses a semiconductor device wherein the connection part includes metal or polysilicon (23, par. 0035-0036) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3-6, 8-11, and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi in view of Ebiike et al. (2019/0348524, hereafter Ebiike) . Regarding claim 3 , Nishiguchi discloses a semiconductor device wherein: the connection part (35c, Fig. 8, par. 0071) is connected to one end part of the carrier conduction part (35, Fig. 8, par. 0071) and is provided in a first connection region; and the first connection region (31, Fig. 8) is provided in the semiconductor layer (10, Fig. 1, par. 0035) and extends in the first direction from one end part of the second semiconductor region in the second direction to the first electrode (20, Fig. 1). Nishiguchi fails to disclose, which is a semiconductor region of the second conductivity type. However, Ebiike teaches which is a semiconductor region of the second conductivity type (15, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a connection region that is a semiconductor region in order to stabilize switching characteristics and bridge the buried conductive region to surface contacts, allowing current to flow vertically. Regarding claim 4 , Nishiguchi fails to disclose a semiconductor device further comprising a second connection part configured to electrically connect the other end part of the carrier conduction part to the first electrode without penetrating the third semiconductor region and provided in a second connection region which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode. However, Ebiike teaches a semiconductor device further comprising a second connection part (15 left, Fig. 1) configured to electrically connect the other end part of the carrier conduction part (13, Fig. 1) to the first electrode (24, Fig. 1) without penetrating the third semiconductor region (14, Fig. 1) and provided in a second connection region (15, Fig. 1, par. 0036) which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer (10, Fig. 1) and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode (Fig 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a second connection and connection region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 5 , Nishiguchi fails to disclose a semiconductor device wherein the first connection region and the second connection region include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region. However, Ebiike teaches a semiconductor device wherein the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1) include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region (13, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing connection regions with the same impurity type as the second semiconductor region in order to ensure an unimpeded, low-resistance electrical path and preventing undesirable p-n junctions. Regarding claim 6 , Nishiguchi discloses a connection part (35c, Fig. 8) provided in the connection region (31, Fig. 8) and configured to electrically connect the carrier conduction part (35, Fig. 8) to the first electrode (20, Fig. 8). NIshiguchi fails to disclose a semiconductor device further comprising: a third connection region provided in the semiconductor layer, located between the first connection region and the second connection region, sandwiched between the third semiconductor regions, and connecting the second semiconductor region to the first electrode; and a third. However, Ebiike teaches a semiconductor device further comprising: a third connection region (15 middle, Fig. 1) provided in the semiconductor layer (10, Fig. 1), located between the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1), sandwiched between the third semiconductor regions (14, Fig. 1), and connecting the second semiconductor region (13, Fig. 1) to the first electrode (24, Fig. 1); and a third (15 middle, Fig. 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a third connecting part and region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 8 , Nishiguchi discloses a semiconductor device wherein: the connection part (35c, Fig. 8, par. 0071) is connected to one end part of the carrier conduction part (35, Fig. 8, par. 0071) and is provided in a first connection region; and the first connection region (31, Fig. 8) is provided in the semiconductor layer (10, Fig. 1, par. 0035) and extends in the first direction from one end part of the second semiconductor region in the second direction to the first electrode (20, Fig. 1). Nishiguchi fails to disclose, which is a semiconductor region of the second conductivity type. However, Ebiike teaches which is a semiconductor region of the second conductivity type (15, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a connection region that is a semiconductor region in order to stabilize switching characteristics and bridge the buried conductive region to surface contacts, allowing current to flow vertically. Regarding claim 9 , Nishiguchi fails to disclose a semiconductor device further comprising a second connection part configured to electrically connect the other end part of the carrier conduction part to the first electrode without penetrating the third semiconductor region and provided in a second connection region which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode. However, Ebiike teaches a semiconductor device further comprising a second connection part (15 left, Fig. 1) configured to electrically connect the other end part of the carrier conduction part (13, Fig. 1) to the first electrode (24, Fig. 1) without penetrating the third semiconductor region (14, Fig. 1) and provided in a second connection region (15, Fig. 1, par. 0036) which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer (10, Fig. 1) and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode (Fig 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a second connection and connection region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 10 , Nishiguchi fails to disclose a semiconductor device wherein the first connection region and the second connection region include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region. However, Ebiike teaches a semiconductor device wherein the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1) include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region (13, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing connection regions with the same impurity type as the second semiconductor region in order to ensure an unimpeded, low-resistance electrical path and preventing undesirable p-n junctions. Regarding claim 11 , Nishiguchi discloses a connection part (35c, Fig. 8) provided in the connection region (31, Fig. 8) and configured to electrically connect the carrier conduction part (35, Fig. 8) to the first electrode (20, Fig. 8). NIshiguchi fails to disclose a semiconductor device further comprising: a third connection region provided in the semiconductor layer, located between the first connection region and the second connection region, sandwiched between the third semiconductor regions, and connecting the second semiconductor region to the first electrode; and a third. However, Ebiike teaches a semiconductor device further comprising: a third connection region (15 middle, Fig. 1) provided in the semiconductor layer (10, Fig. 1), located between the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1), sandwiched between the third semiconductor regions (14, Fig. 1), and connecting the second semiconductor region (13, Fig. 1) to the first electrode (24, Fig. 1); and a third (15 middle, Fig. 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a third connecting part and region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 13 , Nishiguchi discloses a semiconductor device wherein: the connection part (35c, Fig. 8, par. 0071) is connected to one end part of the carrier conduction part (35, Fig. 8, par. 0071) and is provided in a first connection region; and the first connection region (31, Fig. 8) is provided in the semiconductor layer (10, Fig. 1, par. 0035) and extends in the first direction from one end part of the second semiconductor region in the second direction to the first electrode (20, Fig. 1). Nishiguchi fails to disclose, which is a semiconductor region of the second conductivity type. However, Ebiike teaches which is a semiconductor region of the second conductivity type (15, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a connection region that is a semiconductor region in order to stabilize switching characteristics and bridge the buried conductive region to surface contacts, allowing current to flow vertically. Regarding claim 14 , Nishiguchi fails to disclose a semiconductor device further comprising a second connection part configured to electrically connect the other end part of the carrier conduction part to the first electrode without penetrating the third semiconductor region and provided in a second connection region which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode. However, Ebiike teaches a semiconductor device further comprising a second connection part (15 left, Fig. 1) configured to electrically connect the other end part of the carrier conduction part (13, Fig. 1) to the first electrode (24, Fig. 1) without penetrating the third semiconductor region (14, Fig. 1) and provided in a second connection region (15, Fig. 1, par. 0036) which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer (10, Fig. 1) and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode (Fig 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a second connection and connection region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 15 , Nishiguchi fails to disclose a semiconductor device wherein the first connection region and the second connection region include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region. However, Ebiike teaches a semiconductor device wherein the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1) include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region (13, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing connection regions with the same impurity type as the second semiconductor region in order to ensure an unimpeded, low-resistance electrical path and preventing undesirable p-n junctions. Regarding claim 16 , Nishiguchi discloses a semiconductor device wherein: the connection part (35c, Fig. 8, par. 0071) is connected to one end part of the carrier conduction part (35, Fig. 8, par. 0071) and is provided in a first connection region; and the first connection region (31, Fig. 8) is provided in the semiconductor layer (10, Fig. 1, par. 0035) and extends in the first direction from one end part of the second semiconductor region in the second direction to the first electrode (20, Fig. 1). Nishiguchi fails to disclose, which is a semiconductor region of the second conductivity type. However, Ebiike teaches which is a semiconductor region of the second conductivity type (15, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a connection region that is a semiconductor region in order to stabilize switching characteristics and bridge the buried conductive region to surface contacts, allowing current to flow vertically. Regarding claim 17 , Nishiguchi fails to disclose a semiconductor device further comprising a second connection part configured to electrically connect the other end part of the carrier conduction part to the first electrode without penetrating the third semiconductor region and provided in a second connection region which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode. However, Ebiike teaches a semiconductor device further comprising a second connection part (15 left, Fig. 1) configured to electrically connect the other end part of the carrier conduction part (13, Fig. 1) to the first electrode (24, Fig. 1) without penetrating the third semiconductor region (14, Fig. 1) and provided in a second connection region (15, Fig. 1, par. 0036) which is the semiconductor region of the second conductivity type, wherein the second connection region is provided in the semiconductor layer (10, Fig. 1) and extends in the first direction from the other end part of the second semiconductor region in the second direction to the first electrode (Fig 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a second connection and connection region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds. Regarding claim 18 , Nishiguchi fails to disclose a semiconductor device wherein the first connection region and the second connection region include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region. However, Ebiike teaches a semiconductor device wherein the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1) include the semiconductor of the second conductivity type having the impurity concentration of the second conductivity type equal to the impurity concentration of the second conductivity type of the second semiconductor region (13, Fig. 1, par. 0036). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing connection regions with the same impurity type as the second semiconductor region in order to ensure an unimpeded, low-resistance electrical path and preventing undesirable p-n junctions. Regarding claim 19 , Nishiguchi discloses a connection part (35c, Fig. 8) provided in the connection region (31, Fig. 8) and configured to electrically connect the carrier conduction part (35, Fig. 8) to the first electrode (20, Fig. 8). NIshiguchi fails to disclose a semiconductor device further comprising: a third connection region provided in the semiconductor layer, located between the first connection region and the second connection region, sandwiched between the third semiconductor regions, and connecting the second semiconductor region to the first electrode; and a third. However, Ebiike teaches a semiconductor device further comprising: a third connection region (15 middle, Fig. 1) provided in the semiconductor layer (10, Fig. 1), located between the first connection region (15 right, Fig. 1) and the second connection region (15 left, Fig. 1), sandwiched between the third semiconductor regions (14, Fig. 1), and connecting the second semiconductor region (13, Fig. 1) to the first electrode (24, Fig. 1); and a third (15 middle, Fig. 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishiguchi with Ebiike by providing a third connecting part and region in order to minimize parasitic resistance and voltage drops across the buried layer and ensure faster switching speeds . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kobayashi (20180083137), pertaining to connecting parts and regions. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/625,761 Page 2 Art Unit: 2817 Application/Control Number: 18/625,761 Page 3 Art Unit: 2817 Application/Control Number: 18/625,761 Page 4 Art Unit: 2817 Application/Control Number: 18/625,761 Page 5 Art Unit: 2817 Application/Control Number: 18/625,761 Page 6 Art Unit: 2817 Application/Control Number: 18/625,761 Page 7 Art Unit: 2817 Application/Control Number: 18/625,761 Page 8 Art Unit: 2817 Application/Control Number: 18/625,761 Page 9 Art Unit: 2817 Application/Control Number: 18/625,761 Page 10 Art Unit: 2817 Application/Control Number: 18/625,761 Page 11 Art Unit: 2817 Application/Control Number: 18/625,761 Page 12 Art Unit: 2817 Application/Control Number: 18/625,761 Page 13 Art Unit: 2817 Application/Control Number: 18/625,761 Page 14 Art Unit: 2817 Application/Control Number: 18/625,761 Page 15 Art Unit: 2817 Application/Control Number: 18/625,761 Page 16 Art Unit: 2817 Application/Control Number: 18/625,761 Page 17 Art Unit: 2817
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