DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on September 30, 2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yim (US 2021/0257305 A1).
Claim 1, Yim discloses an apparatus (package on package 1000 is an apparatus, hereinafter, apparatus 1000, [0142], Fig. 11), comprising:
a substrate interposer (supporting wiring layer 250 is a substrate interposer, hereinafter, substrate interposer 250, [0127], Fig. 15) having a top surface and a bottom surface (substrate interposer 250 has a top surface and a bottom surface, [0128], Fig. 15), the substrate interposer 250 having a plurality of electrical connections (substrate interposer 250 includes supporting wiring structure 270 which is a plurality of electrical connections, hereinafter, plurality of electrical connections 270, [0128], Fig. 15) from a first set of electrical contacts (a plurality of external connection terminals 190 are a first set of electrical contacts, hereinafter, first set of electrical contacts 190, [0129], Fig. 15) on the bottom surface of the substrate interposer 250, through the substrate interposer 250, to the top surface of the substrate interposer 250 (substrate interposer 250 has a plurality of electrical connections 270 from a first set of electrical contacts 190 on the bottom surface of the substrate interposer 250, through the substrate interposer 250, to the top surface of the substrate interposer 250, [0128], Fig. 15);
a plurality of vertical conductors (plurality of connection structures 162 are a plurality of vertical conductors, hereinafter, plurality of vertical conductors 162, [0069], Fig. 15) mounted to the top surface of the substrate interposer 250 and extending in a vertical direction (plurality of vertical conductors 162 are mounted to the top surface of the substrate interposer 250 and extending in a vertical direction, [0069], Fig. 15), each vertical conductor in the plurality of vertical conductors 162 electrically connected to one electrical connection from the plurality of electrical connections 270 provided by the substrate interposer 250 (each vertical conductor in the plurality of vertical conductors 162 electrically connected to one electrical connection from the plurality of electrical connections 270 provided by the substrate interposer 250, [0127], Fig. 15);
a semiconductor die (semiconductor chip 100 Is a semiconductor die, hereinafter, semiconductor die 100, [0029], Fig. 15), disposed above the top surface of the substrate interposer 250 (semiconductor die 100 is disposed above the top surface of the substrate interposer 250, [0029], Fig. 15), and having a plurality of die contacts (plurality of chip connection pads 120 are a plurality of die contacts, hereinafter, plurality of die contacts 120, [0033], Fig. 15) disposed on a top surface of the semiconductor die 100 (a plurality of die contacts 120 are disposed on a top surface of the semiconductor die 100 (i.e. as semiconductor substrate 110 is on the top surface of the substrate interposer 250, semiconductor die 100 is vertically inverted), [0033], Fig. 15); and
a first metallization structure (cover wiring layer 300 is a first metallization structure, hereinafter, first metallization structure 300, [0114], Fig. 15), disposed above the semiconductor die 100 and the plurality of vertical conductors 162 (first metallization structure 300 is disposed above the semiconductor die 100 and the plurality of vertical conductors 162, [0033], Fig. 15), having at least one electrical connection to each of the plurality of die contacts 120 and to each of the plurality of vertical conductors 162 (first metallization structure 300 has at least one electrical connection to each of the plurality of die contacts 120 and to each of the plurality of vertical conductors 162, [0074], Fig. 15), and providing an electrical connection to a second set of electrical contacts (plurality of wiring patterns 342 are a second set of electrical contacts, hereinafter, second set of electrical contacts 342, [0143], Fig. 15) on a top surface of the first metallization structure 300 (second set of electrical contacts 342 are on a top surface of the first metallization structure 300, [0143], Fig. 15),
wherein the semiconductor die 110 and the plurality of vertical conductors 162 are contained within a layer (semiconductor die 110 and the plurality of vertical conductors 162 are contained within the expanded layer 160, hereinafter layer 160, [0019], Fig. 15), disposed between the top surface of the substrate interposer 250 and a bottom surface of the first metallization structure 300 (layer 160 is disposed between the top surface of the substrate interposer 250 and a bottom surface of the first metallization structure 300, [0019], Fig. 15), comprising a molding compound (layer 160 further comprises filling portion 164 which includes a molding compound (i.e. epoxy mold compound), [0037], Fig. 15).
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Fig. 15 (Yim) – Illustrates a semiconductor die 100 disposed on substrate interposer 250 having a plurality of electrical connections 270 from a first set of electrical contacts 190 on the bottom surface of the substrate interposer 250, through the substrate interposer 250, to the top surface of the substrate interposer 250. The substrate interposer 250 is further electrically connected with an above-lying semiconductor device and mounted on an under-lying printed circuit board (PCB).
Claim 2, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses wherein the substrate interposer 250 comprises one or more vertically stacked layers (substrate interposer 250 further comprises a multi-layered printed circuit board, [0127], Fig. 15), each layer comprising a glass fiber core, a laminate core, an Ajinomoto build-up film core, or a prepreg core (each layer stacked forms a multi-layered printed circuit board and may utilize a glass fiber core, a laminate core, an Ajinomoto build-up film core, or a prepreg core, [0127], Fig. 15), and each layer comprising a conducting structure that forms a portion of the plurality of electrical connections 270 within the substrate interposer 250 (each layer comprises a conducting structure that forms a portion of the plurality of electrical connections 270 within the substrate interposer 250).
Claim 3, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses further comprising a plurality of ball contacts (plurality of package connection terminals 460 are a plurality of ball contacts, hereinafter, plurality of ball contacts 460, [0143], Fig. 15) mounted to the second set of electrical contacts 342 on the top surface of the first metallization structure 300 (plurality of ball contacts 460 are mounted to the second set of electrical contacts 342 on the top surface of the first metallization structure 300, [0143], Fig. 15).
Claim 4, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses wherein the first metallization structure 300 comprises a redistribution layer (RDL) structure comprising one or more polyimide layers (first metallization structure 300 is formed in the same manner as redistribution layer 140 and includes a redistribution layer (RDL) structure, hereinafter, RDL structure 300, wherein RDL structure 300 further comprises one or more polyimide layers, [0028], Fig. 15).
Claim 5, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses comprising at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 (at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300, [0057], Fig. 15).
Claim 6, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses comprising at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one die contact of the plurality of die contacts 120 (at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one die contact of the plurality of die contacts 120, [0074], Fig. 15).
Claim 7, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses comprising at least one electrical connection between at one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 and at least one die contact of the plurality of die contacts 120 (at least one electrical connection between at one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 and at least one die contact of the plurality of die contacts 120, [0074], Fig. 15).
Claim 8, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses wherein at least one vertical conductor of the plurality of vertical conductors 162 comprises a wire bond or a copper pin (at least one vertical conductor of the plurality of vertical conductors 162 comprises a copper pin, [0022], Fig. 15).
Claim 9, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses wherein a thickness of the substrate interposer 250 is in a range from 50μm to 150μm (a thickness of the substrate interposer 250 is in a range from 90 μm to 150 μm (i.e. first thickness T1a), [0132], Figs. 9 and 15).
Claim 10, Yim discloses the apparatus (apparatus 1000, [0142], Fig. 11) of claim 1.
Yim discloses wherein a thickness of the first metallization structure 300 is in a range from 5μm to 40μm (a thickness of the first metallization structure 300 is in a range from 20 μm to 40 μm (i.e. second thickness T2a), [0132], Figs. 9 and 15).
Claim 11, Yim discloses a method for fabricating an apparatus (package on package 1000 is an apparatus, hereinafter, apparatus 1000, [0142], Fig. 11), the method comprising:
providing a substrate interposer (supporting wiring layer 250 is a substrate interposer, hereinafter, substrate interposer 250, [0127], Fig. 15) having a top surface and a bottom surface (substrate interposer 250 has a top surface and a bottom surface, [0128], Fig. 15), the substrate interposer 250 having a plurality of electrical connections (substrate interposer 250 includes supporting wiring structure 270 which is a plurality of electrical connections, hereinafter, plurality of electrical connections 270, [0128], Fig. 15) from a first set of electrical contacts (a plurality of external connection terminals 190 are a first set of electrical contacts, hereinafter, first set of electrical contacts 190, [0129], Fig. 15) on the bottom surface of the substrate interposer 250, through the substrate interposer 250, to the top surface of the substrate interposer 250 (substrate interposer 250 has a plurality of electrical connections 270 from a first set of electrical contacts 190 on the bottom surface of the substrate interposer 250, through the substrate interposer 250, to the top surface of the substrate interposer 250, [0128], Fig. 15);
forming, on the top surface of the substrate interposer 250, a plurality of vertical conductors (plurality of connection structures 162 are a plurality of vertical conductors, hereinafter, plurality of vertical conductors 162, [0069], Fig. 15) extending in a vertical direction (plurality of vertical conductors 162 are mounted to the top surface of the substrate interposer 250 and extending in a vertical direction, [0069], Fig. 15), each vertical conductor in the plurality of vertical conductors 162 electrically connected to one electrical connection from the plurality of electrical connections 270 provided by the substrate interposer 250 (each vertical conductor in the plurality of vertical conductors 162 electrically connected to one electrical connection from the plurality of electrical connections 270 provided by the substrate interposer 250, [0127], Fig. 15);
mounting a semiconductor die (semiconductor chip 100 Is a semiconductor die, hereinafter, semiconductor die 100, [0029], Fig. 15) above the top surface of the substrate interposer 250 (semiconductor die 100 is disposed above the top surface of the substrate interposer 250, [0029], Fig. 15), the semiconductor die 100 having a plurality of die contacts (plurality of chip connection pads 120 are a plurality of die contacts, hereinafter, plurality of die contacts 120, [0033], Fig. 15) disposed on a top surface of the semiconductor die 100 (a plurality of die contacts 120 are disposed on a top surface of the semiconductor die 100 (i.e. as semiconductor substrate 110 is on the top surface of the substrate interposer 250, semiconductor die 100 is vertically inverted), [0033], Fig. 15);
encasing the plurality of vertical conductors 162 and the semiconductor die 110 in a protective layer (semiconductor die 110 and the plurality of vertical conductors 162 are contained within the expanded layer 160, hereinafter, protective layer 160, [0019], Fig. 15) comprising a molding compound such that the plurality of vertical conductors 162 and the plurality of die contacts 120 remain exposed (protective layer 160 further comprises filling portion 164 which includes a molding compound (i.e. epoxy mold compound) such that the plurality of vertical conductors 162 and the plurality of die contacts 120 remain exposed, [0037], Fig. 15); and
forming a first metallization structure (cover wiring layer 300 is a first metallization structure, hereinafter, first metallization structure 300, [0114], Fig. 15) on a top surface of the protective layer 160 (first metallization structure 300 is on a top surface of the protective layer 160, [0114], Fig. 15), the first metallization structure 300 having at least one electrical connection to each of the plurality of die contacts 120 and to each of the plurality of vertical conductors 162 (first metallization structure 300 has at least one electrical connection to each of the plurality of die contacts 120 and to each of the plurality of vertical conductors 162, [0074], Fig. 15), and having an electrical connection to a second set of electrical contacts on a top surface of the first metallization structure 300 (plurality of wiring patterns 342 are a second set of electrical contacts, hereinafter, second set of electrical contacts 342, [0143], Fig. 15) on a top surface of the first metallization structure 300 (second set of electrical contacts 342 are on a top surface of the first metallization structure 300, [0143], Fig. 15).
Claim 12, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses wherein providing the substrate interposer 250 comprises providing one or more vertically stacked layers (substrate interposer 250 further comprises a multi-layered printed circuit board, [0127], Fig. 15), each layer comprising a glass fiber core, a laminate core, an Ajinomoto build-up film core, or a prepreg core (each layer stacked forms a multi-layered printed circuit board and may utilize a glass fiber core, a laminate core, an Ajinomoto build-up film core, or a prepreg core, [0127], Fig. 15), and each layer comprising a conducting structure that forms a portion of the plurality of electrical connections 270 within the substrate interposer 250 (each layer comprises a conducting structure that forms a portion of the plurality of electrical connections 270 within the substrate interposer 250).
Claim 13, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses further comprising a plurality of ball contacts (plurality of package connection terminals 460 are a plurality of ball contacts, hereinafter, plurality of ball contacts 460, [0143], Fig. 15) mounted to the second set of electrical contacts 342 on the top surface of the first metallization structure 300 (plurality of ball contacts 460 are mounted to the second set of electrical contacts 342 on the top surface of the first metallization structure 300, [0143], Fig. 15).
Claim 14, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses wherein forming the first metallization structure 300 comprises a redistribution layer (RDL) structure comprising one or more polyimide layers (first metallization structure 300 is formed in the same manner as redistribution layer 140 and includes a redistribution layer (RDL) structure, hereinafter, RDL structure 300, wherein RDL structure 300 further comprises one or more polyimide layers, [0028], Fig. 15).
Claim 15, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses resulting in at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 (at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300, [0057], Fig. 15).
Claim 16, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses resulting in at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one die contact of the plurality of die contacts 120 (at least one electrical connection between at one electrical contact of the first set of electrical contacts 190 on the bottom surface of the substrate interposer 250 and at least one die contact of the plurality of die contacts 120, [0074], Fig. 15).
Claim 17, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses resulting in at least one electrical connection between at one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 and at least one die contact of the plurality of die contacts 120 (at least one electrical connection between at one electrical contact of the second set of electrical contacts 342 on a top surface of the first metallization structure 300 and at least one die contact of the plurality of die contacts 120, [0074], Fig. 15).
Claim 18, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses wherein at least one vertical conductor of the plurality of vertical conductors 162 comprises a wire bond or a copper pin (at least one vertical conductor of the plurality of vertical conductors 162 comprises a copper pin, [0022], Fig. 15).
Claim 19, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses wherein a thickness of the substrate interposer 250 is in a range from 50μm to 150μm (a thickness of the substrate interposer 250 is in a range from 90 μm to 150 μm (i.e. first thickness T1a), [0132], Figs. 9 and 15).
Claim 20, Yim discloses the method (apparatus 1000, [0142], Fig. 11) of claim 11.
Yim discloses wherein a thickness of the first metallization structure 300 is in a range from 5μm to 40μm (a thickness of the first metallization structure 300 is in a range from 20 μm to 40 μm (i.e. second thickness T2a), [0132], Figs. 9 and 15).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jeng (US 2021/0320069 A1) discloses a package structure 133 further including a substrate interposer 112, semiconductor die 108, metallization structures 102 and 136/137¸ vertical conductors 116’/206, and ball connectors 140, wherein an additional element 134 may be above-lying and an under-lying substrate 204.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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