DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
With respect to Applicant’s amendment to Claims 1, 11 and 18 in regards to minor informalities, objection with respect to the same has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 11, 14-16, 18 and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ning et al. (US PGPUB 2023/0054426) in view of Best (US PGPUB 2016/0147481), Takano (US PGPUB 2023/0214136) and Oldham, III (US Patent 3,668,632).
With regard to Claim 1, Ning teaches a memory circuit, comprising:
a memory array comprising a plurality of memory bit cells ([0007] “The present disclosure provides a read-write method, when a write operation is performed on a memory.” [0021] “A basic memory cell of DRAM includes a transistor and a capacitor.” [0022] “if the data to be written is 8-bit data 10010010…”);
a data pattern detector configured to ([0018] “FIG. 1 is a flowchart of a read-write method according to a first embodiment of the present disclosure. Referring to FIG. 1, the read-write method includes the following steps:”):
(ii) identify a first number of a first subset of the data bits that are each equal to a first logic state and a second number of a second subset of the data bits that are each equal to a second logic state ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.”),
wherein the first logic state is a logic 1 and the second logic state is a logic 0 ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.” [0020] “The first value and the second value are binary numbers 1 and 0 indicating a storage state of charges stored in the memory.”);
(iv) in response to determining that the first number of the first subset having the first logic state of logic 1 is larger than the one half of the total number of the data bits, selectively adjust respective logic states of the data bits ([0023] “If the first values are more than the second values in the data to be written, that is, the number of first values is greater than the number of second values, the data to be written is inverted…,” wherein determining that the number of “first values” is greater than the number of “second values” is mathematically equivalent to positively determining that the number of “first values” is “larger than the one half of the total number of the data bits” since the only two possible values for the associated data bits are either the “first value” or the “second value”.); and
write the selectively adjusted logic states of the data bits into the plurality of memory bit cells, respectively ([0023] “the data to be written is inverted and then stored.”).
With further regard to claim 1, Ning does not teach the data receiving and write driver as described in claim 1. Best teaches the memory circuit comprising:
a data pattern detector configured to: (i) receive a plurality of data bits ([0045] “At 702, the method 700 includes receiving non-DBI encoded groups of m-bit data signals”); and
a write driver configured to write ([0021] “DDR3 memory includes Stub Series Terminated Logic (SSTL) signaling that consumes power when it transmits both high and low electrical states. FIG. 3A is a diagram of a DDR3 circuit 300, in which SSTL signaling incurs a drive current I2,” see Fig. 3A showing an “Output driver”. [0037] “Once controller 501 configures DIMM 500 to operate in ×8 mode, controller 501 further may configure buffer circuit 503 of DIMM 500 to operate in DBI mode for both read and write operations.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning with the data receiving and write driver as taught by Best in order “to save power when controller 401 enables DBI [Data Bus Inversion] support” (Best [0034]).
With further regard to claim 1, Ning in view of Best does not teach the threshold value determination as described in claim 1. Takano teaches
(iii) compare the first number with a threshold value, wherein the threshold value is one half of a total number of the data bits ([0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best with the threshold value determination as taught by Takano “so that the power consumption during the transmission of the second data can be reduced” (Takano [0147]).
With further regard to claim 1, Ning in view of Best and Takano does not teach the pattern detector circuit composition as described in claim 1. Oldham teaches
wherein the data pattern detector includes a counter and at least one comparator, the counter comprising a plurality of half adders arranged in a first level to receive respective pairs of data bits from the plurality of data bits, and a plurality of full adders arranged in one or more subsequent levels to sum outputs of the half adders (Col. 9 ll. 61-67: “Because of the nature of the start pattern, the line start detector detects the line start pattern if 11 or more of the 14 bits of the line start pattern are correct... read data is inserted into shift register 101. The line start detector is essentially an adder. It counts the number of bits not corresponding to the line start pattern.” Col. 9 ll. 72-73: “In FIG. 7, blocks 249, 251, 253, 255, 257, 259, 261 are half-adders.” Col. 10 ll. 14-15: “Blocks 263, 265, 267, 269, 271 add their respective two input pairs,” wherein “Blocks 263, 265, 267” are the “plurality of full adders” and further wherein Fig. 7 of Oldham shows the arrangement of “half-adders” in a “first level” and “full adders” in “one or more subsequent levels to sum outputs of the half adders.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best and Takano with the pattern detector circuit composition as taught by Oldham in order “to provide a new and improved system for error detection and correction” (Oldham Col. 1 ll. 41-43).
With regard to Claim 4, Ning in view of Best, Takano and Oldham teaches all the limitations of Claim 1 as described above. Takano further teaches wherein the data pattern detector is further configured to:
(i) determine the first number ([0025] “The encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group” [0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400,” wherein the “DBI encoder” determines the “first number” as further discussed below.);
(ii) in response to the first number being larger than the threshold value, logically inverse the respective logic states of the data bits ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted and thus the number of 1's of the second data 720 becomes small,” wherein the total number of bits is 4 and as such the “threshold value” is 2, i.e. half of 4.); and
(iii) in response to the first number being less than the threshold value, logically maintain the respective logic states of the data bits ([0088] “a flag of the value of 0 is added to the second data 720 in which 0 and 1 are not inverted,” see for example the Data Values “A-1” through “C-1” in Fig. 5 of Takano, wherein the number of “1” logic states is less than 2 and the logic states of the data bits are logically maintained as shown in the respective Data Values “A-2” through “C-2”.).
With regard to claim 5, Ning in view of Best, Takano and Oldham teaches all the limitations of claim 4 as described above. Takano further teaches
wherein the data pattern detector is further configured to determine the threshold value as the one half of the total number of the data bits ([0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400,” wherein the “DBI encoder” performs the functions of the “data pattern detector”. [0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
With regard to claim 6, Ning in view of Best, Takano and Oldham teaches all the limitations of claim 4 as described above. Takano further teaches
wherein the threshold value is preconfigured as the one half of the total number of the data bits ([0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400.” [0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
With regard to Claim 7, Ning in view of Best, Takano and Oldham teaches all the limitations of Claim 4 as described above. Takano further teaches wherein the data pattern detector is further configured to provide a flag bit indicating whether the first number is larger or less than the threshold value ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted.”).
With regard to Claim 11, Ning teaches a memory circuit, comprising:
a memory array comprising a plurality of memory bit cells ([0007] “The present disclosure provides a read-write method, when a write operation is performed on a memory.” [0021] “A basic memory cell of DRAM includes a transistor and a capacitor.” [0022] “if the data to be written is 8-bit data 10010010…”);
a data pattern detector configured to ([0018] “FIG. 1 is a flowchart of a read-write method according to a first embodiment of the present disclosure. Referring to FIG. 1, the read-write method includes the following steps:”):
(i) identify a first number of a first subset of a plurality of data bits that are each equal to a first logic state ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.”),
wherein the first logic state is a logic 1 ([0020] “The first value and the second value are binary numbers 1 and 0 indicating a storage state of charges stored in the memory.”), and
(ii) in response to determining that the first number of the first subset having the first logic state of logic 1 is larger than the one half of the total number of the data bits, logically invert respective logic states of the data bits ([0023] “If the first values are more than the second values in the data to be written, that is, the number of first values is greater than the number of second values, the data to be written is inverted…,” wherein determining that the number of “first values” is greater than the number of “second values” is mathematically equivalent to positively determining that the number of “first values” is “larger than the one half of the total number of the data bits” since the only two possible values for the associated data bits are either the “first value” or the “second value”.); and
write the logically inverted logic states of the data bits into the plurality of memory bit cells, respectively ([0023] “the data to be written is inverted and then stored.”).
With further regard to claim 11, Ning does not teach the write driver as described in claim 11. Best teaches the memory circuit comprising:
a write driver configured to write ([0021] “DDR3 memory includes Stub Series Terminated Logic (SSTL) signaling that consumes power when it transmits both high and low electrical states. FIG. 3A is a diagram of a DDR3 circuit 300, in which SSTL signaling incurs a drive current I2,” see Fig. 3A showing an “Output driver”. [0037] “Once controller 501 configures DIMM 500 to operate in ×8 mode, controller 501 further may configure buffer circuit 503 of DIMM 500 to operate in DBI mode for both read and write operations.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning with the write driver as taught by Best in order “to save power when controller 401 enables DBI [Data Bus Inversion] support” (Best [0034]).
With further regard to claim 11, Ning in view of Best does not teach the threshold value determination as described in claim 11. Takano teaches
(i) identify a first number of a first subset of a plurality of data bits that are each equal to a first logic state being larger than a threshold value, wherein the threshold value is one half of a total number of the data bits ([0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best with the threshold value determination as taught by Takano “so that the power consumption during the transmission of the second data can be reduced” (Takano [0147]).
With further regard to claim 11, Ning in view of Best and Takano does not teach the pattern detector circuit composition as described in claim 11. Oldham teaches
wherein the data pattern detector includes a counter and at least one comparator, the counter comprising a plurality of half adders arranged in a first level to receive respective pairs of data bits from the plurality of data bits, and a plurality of full adders arranged in one or more subsequent levels to sum outputs of the half adders (Col. 9 ll. 61-67: “Because of the nature of the start pattern, the line start detector detects the line start pattern if 11 or more of the 14 bits of the line start pattern are correct... read data is inserted into shift register 101. The line start detector is essentially an adder. It counts the number of bits not corresponding to the line start pattern.” Col. 9 ll. 72-73: “In FIG. 7, blocks 249, 251, 253, 255, 257, 259, 261 are half-adders.” Col. 10 ll. 14-15: “Blocks 263, 265, 267, 269, 271 add their respective two input pairs,” wherein “Blocks 263, 265, 267” are the “plurality of full adders” and further wherein Fig. 7 of Oldham shows the arrangement of “half-adders” in a “first level” and “full adders” in “one or more subsequent levels to sum outputs of the half adders.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best and Takano with the pattern detector circuit composition as taught by Oldham in order “to provide a new and improved system for error detection and correction” (Oldham Col. 1 ll. 41-43).
With regard to Claims 14-16, these claims are equivalent in scope to Claims 5-7 rejected above, merely having a different independent claim type, and as such Claims 14-16 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 5-7.
With regard to Claims 18 and 20-23, these claims are equivalent in scope to Claims 11 and 14-16 rejected above, merely having a different independent claim type, and as such Claims 18 and 20-23 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 11 and 14-16.
Claims 8-10, 17 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ning in view of Best, Takano and Oldham as applied to Claims 7, 16 and 20 above, and further in view of Kim et al. (US PGPUB 2014/0016404).
With regard to claim 8, Ning in view of Best, Takano and Oldham teaches all the limitations of claim 7 as described above. Ning in view of Best, Takano and Oldham does not teach the threshold value determination as described in claim 8. Kim teaches further comprising:
a read driver configured to read, from the memory bit cells, the logic states of the data bits ([0293] “Data read from the MRAM cell array 425....” [0236] “The MRAM 322 includes… a second output driver 324b… The fourth buffer 326b stores the second data D1, and the second output driver 324b transmits the second data D1 stored in the fourth buffer 326b to the channel 327. The second data D1 transmitted to the channel 327 is received by the first input driver 325b,” wherein the “second output driver 324b” is the “read driver”.); and
a plurality of inverters configured to selectively logically invert the read logic states based on the flag bit ([0361] “The MRAM 550 includes a data comparator 553 and first and second sets of data inverters 554 and 555 (first and second inversion units) in order to control internal I/O data transmission.” [0362] “The first set of data inverters 554 includes circuitry that inverts a phase of nth data from the IOSA 552 when the inversion flag signal IVF is activated.” [0366] “In order to provide a read DBI function, the MRAM 550, when the number of bits of a low level is greater than the number of bits of a high level from among read data applied by the MRAM core block 551, inverts the read data by using the first set of data inverters 554.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best, Takano and Oldham with the read driver and inverters as taught by Kim in order to “provide a write DBI function and a read DBI function in order to minimize bit switching between data words” (Kim [0131]).
With regard to Claim 9, Ning in view of Best, Takano, Oldham and Kim teaches all the limitations of Claim 8 as described above. Takano further teaches wherein the flag bit is equal to a first value when the first number is larger than the threshold value, and the flag bit is equal to a second value when the first number is less than the threshold value ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted... A flag of the value of 1 are added to the second data 720 in which 0 and 1 are inverted, and a flag of the value of 0 is added to the second data 720 in which 0 and 1 are not inverted.”).
With regard to Claim 10, Ning in view of Best, Takano, Oldham and Kim teaches all the limitations of Claim 9 as described above. Kim further teaches wherein the plurality of inverters are activated in response to the flag bit being equal to the first value, and remain deactivated in response to the flag bit being equal to the second value ([0362] “The first set of data inverters 554 includes circuitry that inverts a phase of nth data from the IOSA 552 when the inversion flag signal IVF is activated”).
With regard to Claim 17, this claim is equivalent in scope to Claim 8 rejected above, merely having a different independent claim type, and as such Claim 17 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 8.
With regard to Claims 24-25, these claims are equivalent in scope to Claim 9 rejected above, merely having a different independent claim type, and as such Claims 24-25 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claim 9.
Response to Arguments
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
Response to Arguments
Applicant's arguments, see Pages 7-10 of the Remarks filed 6/23/26, with respect to the rejections under 35 U.S.C. 103 of Claims 1, 11 and 18 have been fully considered but they are not persuasive. With respect to the Applicant’s argument that the newly amended language of Claims 1, 11 and 18 is not taught by the previously cited prior art, this argument has been fully considered but is moot in view of the newly cited Oldham, III (US Patent 3,668,632) reference as discussed above in the respective rejections.
With respect to the Applicant’s further arguments, Page 10 of the Remarks, that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to amended Claims 1, 11 and 18, and as such the Office directs the Applicant to the response above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Chakrabarty et al. (US PGPUB 2022/0066888) discusses a method and system for on-line detection of faults in ReRAM devices, wherein the detection hardware includes use of an adder tree as monitoring circuitry and further wherein the adder tree includes a plurality of half-adders and full-adders arranged in different levels.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J SIMONETTI whose telephone number is (571)270-7702. The examiner can normally be reached Monday-Thursday 10AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 July 25, 2026
Prosecution Insights