DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/17/2026 has been entered.
Response to Amendment
With respect to Applicant’s amendment to Claim 23 in regards to minor informalities, objection with respect to the same has been withdrawn.
Claim Objections
Claims 1-2, 4-12, 14-18 and 20-23 are objected to because of the following informalities:
Claims 1, 11 and 18 recite on Lines 8, 7 and 6 respectively: “the first logic state of the logic 1” which should be “the first logic state of [[the]] logic 1”.
Claims 2, 4-10, 12, 14-17 and 20-23 are also objected to as they depend on at least one of objected Claims 1, 11 and 18.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 11, 14-16, 18 and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ning et al. (US PGPUB 2023/0054426) in view of Best (US PGPUB 2016/0147481) and Takano (US PGPUB 2023/0214136).
With regard to Claim 1, Ning teaches a memory circuit, comprising:
a memory array comprising a plurality of memory bit cells ([0007] “The present disclosure provides a read-write method, when a write operation is performed on a memory.” [0021] “A basic memory cell of DRAM includes a transistor and a capacitor.” [0022] “if the data to be written is 8-bit data 10010010…”);
a data pattern detector configured to ([0018] “FIG. 1 is a flowchart of a read-write method according to a first embodiment of the present disclosure. Referring to FIG. 1, the read-write method includes the following steps:”):
(ii) identify a first number of a first subset of the data bits that are each equal to a first logic state and a second number of a second subset of the data bits that are each equal to a second logic state ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.”),
wherein the first logic state is a logic 1 and the second logic state is a logic 0 ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.” [0020] “The first value and the second value are binary numbers 1 and 0 indicating a storage state of charges stored in the memory.”);
(iv) in response to determining that the first number of the first subset having the first logic state of the logic 1 is larger than the one half of the total number of the data bits, selectively adjust respective logic states of the data bits ([0023] “If the first values are more than the second values in the data to be written, that is, the number of first values is greater than the number of second values, the data to be written is inverted…,” wherein determining that the number of “first values” is greater than the number of “second values” is mathematically equivalent to positively determining that the number of “first values” is “larger than the one half of the total number of the data bits” since the only two possible values for the associated data bits are either the “first value” or the “second value”.); and
write the selectively adjusted logic states of the data bits into the plurality of memory bit cells, respectively ([0023] “the data to be written is inverted and then stored.”).
With further regard to claim 1, Ning does not teach the data receiving and write driver as described in claim 1. Best teaches the memory circuit comprising:
a data pattern detector configured to: (i) receive a plurality of data bits ([0045] “At 702, the method 700 includes receiving non-DBI encoded groups of m-bit data signals”); and
a write driver configured to write ([0021] “DDR3 memory includes Stub Series Terminated Logic (SSTL) signaling that consumes power when it transmits both high and low electrical states. FIG. 3A is a diagram of a DDR3 circuit 300, in which SSTL signaling incurs a drive current I2,” see Fig. 3A showing an “Output driver”. [0037] “Once controller 501 configures DIMM 500 to operate in ×8 mode, controller 501 further may configure buffer circuit 503 of DIMM 500 to operate in DBI mode for both read and write operations.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning with the data receiving and write driver as taught by Best in order “to save power when controller 401 enables DBI [Data Bus Inversion] support” (Best [0034]).
With further regard to claim 1, Ning in view of Best does not teach the threshold value determination as described in claim 1. Takano teaches
(iii) compare the first number with a threshold value, wherein the threshold value is one half of a total number of the data bits ([0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best with the threshold value determination as taught by Takano “so that the power consumption during the transmission of the second data can be reduced” (Takano [0147]).
With regard to Claim 4, Ning in view of Best and Takano teaches all the limitations of Claim 1 as described above. Takano further teaches wherein the data pattern detector is further configured to:
(i) determine the first number ([0025] “The encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group” [0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400,” wherein the “DBI encoder” determines the “first number” as further discussed below.);
(ii) in response to the first number being larger than the threshold value, logically inverse the respective logic states of the data bits ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted and thus the number of 1's of the second data 720 becomes small,” wherein the total number of bits is 4 and as such the “threshold value” is 2, i.e. half of 4.); and
(iii) in response to the first number being less than the threshold value, logically maintain the respective logic states of the data bits ([0088] “a flag of the value of 0 is added to the second data 720 in which 0 and 1 are not inverted,” see for example the Data Values “A-1” through “C-1” in Fig. 5 of Takano, wherein the number of “1” logic states is less than 2 and the logic states of the data bits are logically maintained as shown in the respective Data Values “A-2” through “C-2”.).
With regard to claim 5, Ning in view of Best and Takano teaches all the limitations of claim 4 as described above. Takano further teaches
wherein the data pattern detector is further configured to determine the threshold value as the one half of the total number of the data bits ([0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400,” wherein the “DBI encoder” performs the functions of the “data pattern detector”. [0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
With regard to claim 6, Ning in view of Best and Takano teaches all the limitations of claim 4 as described above. Takano further teaches
wherein the threshold value is preconfigured as the one half of the total number of the data bits ([0080] “The first data 700 stored in the second buffer memory is encoded into the second data 720 by the first DBI encoder 400.” [0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
With regard to Claim 7, Ning in view of Best and Takano teaches all the limitations of Claim 4 as described above. Takano further teaches wherein the data pattern detector is further configured to provide a flag bit indicating whether the first number is larger or less than the threshold value ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted.”).
With regard to Claim 11, Ning teaches a memory circuit, comprising:
a memory array comprising a plurality of memory bit cells ([0007] “The present disclosure provides a read-write method, when a write operation is performed on a memory.” [0021] “A basic memory cell of DRAM includes a transistor and a capacitor.” [0022] “if the data to be written is 8-bit data 10010010…”);
a data pattern detector configured to ([0018] “FIG. 1 is a flowchart of a read-write method according to a first embodiment of the present disclosure. Referring to FIG. 1, the read-write method includes the following steps:”):
(i) identify a first number of a first subset of a plurality of data bits that are each equal to a first logic state ([0019] “When a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined. That is, whether a number of first values is greater than a number of second values in data to be written is determined.”),
wherein the first logic state is a logic 1 ([0020] “The first value and the second value are binary numbers 1 and 0 indicating a storage state of charges stored in the memory.”), and
(ii) in response to determining that the first number of the first subset having the first logic state of the logic 1 is larger than the one half of the total number of the data bits, logically invert respective logic states of the data bits ([0023] “If the first values are more than the second values in the data to be written, that is, the number of first values is greater than the number of second values, the data to be written is inverted…,” wherein determining that the number of “first values” is greater than the number of “second values” is mathematically equivalent to positively determining that the number of “first values” is “larger than the one half of the total number of the data bits” since the only two possible values for the associated data bits are either the “first value” or the “second value”.); and
write the logically inverted logic states of the data bits into the plurality of memory bit cells, respectively ([0023] “the data to be written is inverted and then stored.”).
With further regard to claim 11, Ning does not teach the write driver as described in claim 11. Best teaches the memory circuit comprising:
a write driver configured to write ([0021] “DDR3 memory includes Stub Series Terminated Logic (SSTL) signaling that consumes power when it transmits both high and low electrical states. FIG. 3A is a diagram of a DDR3 circuit 300, in which SSTL signaling incurs a drive current I2,” see Fig. 3A showing an “Output driver”. [0037] “Once controller 501 configures DIMM 500 to operate in ×8 mode, controller 501 further may configure buffer circuit 503 of DIMM 500 to operate in DBI mode for both read and write operations.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning with the write driver as taught by Best in order “to save power when controller 401 enables DBI [Data Bus Inversion] support” (Best [0034]).
With further regard to claim 11, Ning in view of Best does not teach the threshold value determination as described in claim 11. Takano teaches
(i) identify a first number of a first subset of a plurality of data bits that are each equal to a first logic state being larger than a threshold value, wherein the threshold value is one half of a total number of the data bits ([0084] “in FIGS. 5 and 6A to 6C, the first data is subjected to the DBI process to be encoded into the second data, among the data of 4 bits, 0 and 1 are necessarily inverted in data having three or more 1's. That is, among the bits provided in the first data, if bits more than a half are 1, 0 and 1 are necessarily inverted.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best with the threshold value determination as taught by Takano “so that the power consumption during the transmission of the second data can be reduced” (Takano [0147]).
With regard to Claims 14-16, these claims are equivalent in scope to Claims 5-7 rejected above, merely having a different independent claim type, and as such Claims 14-16 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 5-7.
With regard to Claims 18 and 20-23, these claims are equivalent in scope to Claims 11 and 14-16 rejected above, merely having a different independent claim type, and as such Claims 18 and 20-23 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 11 and 14-16.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ning in view of Best and Takano as applied to Claims 1 and 11above, and further in view of Simkins et al. (US PGPUB 2006/0288069).
With regard to claim 2, Ning in view of Best and Takano teaches all the limitations of claim 1 as described above. Ning in view of Best and Takano does not teach the data pattern detector components as described in claim 2. Simkins teaches
wherein the data pattern detector includes a counter that comprises a plurality of adders and at least one comparator ([0032] “FIG. 19 is a schematic of a pattern detector,” wherein Fig. 19 shows ALU 292 and Comparator 295. [0092] “FIG. 11 is an expanded view of ALU 292. The bitwise add circuit 370 includes a multiplexer 612 and a plurality of three bit adders 610-1 to 610-48.” [0127] “in one aspect the pattern detector 1210 compares a 48 bit pattern 1276 with the output 296 of the ALU 292…. The 48 bit output 296 of ALU 292… is also sent to comparator 295 (see FIG. 3). Comparator 295 bitwise XNORs the 48 bit output 296 of ALU 292 with the 48 bit Pattern 1276. Hence if the there is a match in a bit ALU_output[i] with a bit Pattern[i] then the XNOR_result[i] for that bit is 1.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best and Takano with the data pattern detector components as taught by Simkins since “One solution to the increasing demand for more real-time, concurrent arithmetic operations, is to configure the programmable logic and interconnect in a Programmable Logic Device (PLD) with multiple DSP elements, where each element includes one or more multipliers coupled to one or more adders” (Simkins [0005]).
With regard to Claim 12, this claim is equivalent in scope to Claim 2 rejected above, merely having a different independent claim type, and as such Claim 12 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 2.
Claims 8-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ning in view of Best and Takano as applied to Claims 7 and 16 above, and further in view of Kim et al. (US PGPUB 2014/0016404).
With regard to claim 8, Ning in view of Best and Takano teaches all the limitations of claim 7 as described above. Ning in view of Best and Takano does not teach the threshold value determination as described in claim 8. Kim teaches further comprising:
a read driver configured to read, from the memory bit cells, the logic states of the data bits ([0293] “Data read from the MRAM cell array 425....” [0236] “The MRAM 322 includes… a second output driver 324b… The fourth buffer 326b stores the second data D1, and the second output driver 324b transmits the second data D1 stored in the fourth buffer 326b to the channel 327. The second data D1 transmitted to the channel 327 is received by the first input driver 325b,” wherein the “second output driver 324b” is the “read driver”.); and
a plurality of inverters configured to selectively logically invert the read logic states based on the flag bit ([0361] “The MRAM 550 includes a data comparator 553 and first and second sets of data inverters 554 and 555 (first and second inversion units) in order to control internal I/O data transmission.” [0362] “The first set of data inverters 554 includes circuitry that inverts a phase of nth data from the IOSA 552 when the inversion flag signal IVF is activated.” [0366] “In order to provide a read DBI function, the MRAM 550, when the number of bits of a low level is greater than the number of bits of a high level from among read data applied by the MRAM core block 551, inverts the read data by using the first set of data inverters 554.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory circuit as disclosed by Ning in view of Best and Takano with the read driver and inverters as taught by Kim in order to “provide a write DBI function and a read DBI function in order to minimize bit switching between data words” (Kim [0131]).
With regard to Claim 9, Ning in view of Best, Takano and Kim teaches all the limitations of Claim 8 as described above. Takano further teaches wherein the flag bit is equal to a first value when the first number is larger than the threshold value, and the flag bit is equal to a second value when the first number is less than the threshold value ([0088] “For example, by using the conversion table of FIG. 5, ‘0111’ of 4 bits of H-1 of the first data 700 is encoded into ‘1000’ of H-2 of the second data 720, and a flag of a value of 1 is added. In another example, ‘1011’ of 4 bits of L-1 of the first data 700 is encoded into ‘0100’ of L-2 of the second data 720, and a flag of a value of 1 is added. The same applies to the other cases, but in all cases, in the first data 700, data of which the number of 1's is three or more is encoded so that 0 and 1 are necessarily inverted... A flag of the value of 1 are added to the second data 720 in which 0 and 1 are inverted, and a flag of the value of 0 is added to the second data 720 in which 0 and 1 are not inverted.”).
With regard to Claim 10, Ning in view of Best, Takano and Kim teaches all the limitations of Claim 9 as described above. Kim further teaches wherein the plurality of inverters are activated in response to the flag bit being equal to the first value, and remain deactivated in response to the flag bit being equal to the second value ([0362] “The first set of data inverters 554 includes circuitry that inverts a phase of nth data from the IOSA 552 when the inversion flag signal IVF is activated”).
With regard to Claim 17, this claim is equivalent in scope to Claim 8 rejected above, merely having a different independent claim type, and as such Claim 17 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 8.
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but they are not persuasive.
With respect to Applicant’s argument, Page 7-8 of the Remarks, regarding Claim 1 that Ning in view of Best and Brox does not teach, “(iv) in response to determining that the first number of the first subset having the first logic state of the logic 1 is larger than the one half of the total number of the data bits, selectively adjust respective logic states of the data bits”, the Office respectfully disagrees.
Since this claim language was newly added in the most recent claim amendment the Office has cited further disclosure from the Ning reference which teaches said claim language. The Ning reference recites in Paragraph [0023], “If the first values are more than the second values in the data to be written, that is, the number of first values is greater than the number of second values, the data to be written is inverted…,” wherein the Office contends that determining that the number of “first values” is greater than the number of “second values” is mathematically equivalent to positively determining that the number of “first values” is “larger than the one half of the total number of the data bits” since the only two possible values for the associated data bits are either the “first value” or the “second value”.
As such, it has been shown that the Ning reference does in fact teach the newly amended limitation as recited in Claim 1.
With respect to the Applicant’s arguments, Pages 8-9 of the Remarks, that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to amended Claim 1, and as such the Office directs the Applicant to the response above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Hein (US PGPUB 2013/0061006) discloses devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit, including an approach for minimizing the number of logic 1s transmitted over busses by inverting data which has more than half of the total bits being logic 1s.
Lee et al. (“Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction,” 2018) discusses a technique to save energy by reducing the energy-expensive 1 values in the DRAM interface, including discussion regarding the use of Dynamic Bus Inversion (DBI) which inverts data bits when more than half of the data bits are a logical 1 value.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 March 18, 2026